ULTRATHIN MULTILAYER METAL ALLOY LINER FOR NANO CU INTERCONNECTS

• US 20160276280A1
• Filed: 05/10/2016
• Published: 09/22/2016
• Est. Priority Date: 06/08/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: EDELSTEIN, DANIEL, Grill, Alfred, Knupp, Seth L., Nguyen, Son, Nogami, Takeshi, Paruchuri, Vamsi K., Shobha, Hosadurga K., Yang, Chih-Chao
• Granted Patent: US 10,643,890 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: C23C 16/04 Coating on selected surface areas, e.g. using masks
• CPC Class Codes: C23C 16/06 characterised by the deposition of metallic material
• CPC Class Codes: C23C 16/16 from metal carbonyl compounds
• CPC Class Codes: C23C 16/18 from metallo-organic compounds
• CPC Class Codes: C23C 16/30 Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
• CPC Class Codes: C23C 16/45525 Atomic layer deposition [ALD]
• CPC Class Codes: C23C 16/45544 characterized by the apparatus
• CPC Class Codes: C23C 16/505 using radio frequency discharges
• CPC Class Codes: C23C 16/54 Apparatus specially adapted for continuous coating
• CPC Class Codes: C23C 16/56 After-treatment
• CPC Class Codes: H01L 21/28556 by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/28562 Selective deposition
• CPC Class Codes: H01L 21/28568 the conductive layers comprising transition metals H01L21/28518 takes precedence
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/7685 : the layer covering a conductive structure H01L21/76849 takes precedence
• CPC Class Codes: H01L 21/76852 : the layer also covering the sidewalls of the conductive structure
• CPC Class Codes: H01L 21/76862 : Bombardment with particles, e.g. treatment in noble gas plasmas; UV irradiation
• CPC Class Codes: H01L 21/76864 : Thermal treatment
• CPC Class Codes: H01L 21/76879 : by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76883 : Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 23/5226 : Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 : Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53238 : Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Compositions of matter, compounds, articles of manufacture and processes to reduce or substantially eliminate EM and/or stress migration, and/or TDDB in copper interconnects in microelectronic devices and circuits, especially a metal liner around copper interconnects comprise an ultra thin layer or layers of Mn alloys containing at least one of W and/or Co on the metal liner. This novel alloy provides EM and/or stress migration resistance, and/or TDDB resistance in these copper interconnects, comparable to thicker layers of other alloys found in substantially larger circuits and allows the miniaturization of the circuit without having to use thicker EM and/or TDDB resistant alloys previously used thereby enhancing the miniaturization, i.e., these novel alloy layers can be miniaturized along with the circuit and provide substantially the same EM and/or TDDB resistance as thicker layers of different alloy materials previously used that lose some of their EM and/or TDDB resistance when used as thinner layers.

Claims

1. A process comprising:

(a) forming wire embedded in a dielectric layer on a semiconductor substrate, said wire comprising a copper core comprising sidewalls and a bottom of said copper core, a top surface of said wire coplanar with a top surface of said dielectric layer;

(b) forming an electrically conductive alloy liner on said sidewalls based on Mn, with at least one of Co and/or W to minimize or eliminate EM and/or TDDB;

(c) without exposing said substrate to oxygen, forming a dielectric liner over said alloy liner, any exposed portions of said alloy liner, and said dielectric layer.

2. The process of claim 1, wherein:

(b) and (c) are performed in a same chamber of a first deposition tool without removing said substrate from said chamber;

or (b) and (c) are performed in a different chamber or chambers of a second deposition tool without removing said substrate from said tool.

3. The process of claim 1, wherein said liner is formed by either selective chemical vapor deposition or selective atomic layer deposition.

4. The process of claim 1, wherein said liner comprise a Co/Mn, Co/Mn/W, W/Mn, or W/Mn/Co layer and intercalated combinations of Co/Mn/W layers as an alloy of Mn of from about 0.1 to about 20 parts by weight, Co of from about 0 to about 100 parts by weight and W of from about from about 0 to about 100 parts by weight

5. The process of claim 4, wherein said liner comprises an ultra thin metal alloy liner from about 0.3 nm to about 1 nm thick.

6. The process of claim 1, wherein:

(b), (c) and (d) are performed in a same chamber of a first deposition tool without removing said substrate from said chamber;

or (b) and (d) are performed in a first chamber and (c) is performed in a third chamber of a second deposition tool;

or (b), (d) and (c) are performed in different chambers of a third deposition tool.

7. The process of claim 1, further including:

between (a) and (b), recessing a top surface of said copper core below said top surface of said dielectric layer.

8. The process of claim 1, further comprising conducting the process in an integrated in-situ apparatus having from about 3 to about 5 chambers including a lower chamber and conducting said deposition by means of said apparatus to deposit at least one of multilayer metals, or metal alloys or dielectrics and optionally performing a cure treatment in said lower chamber.

15. The process of claim 1 further comprising further downstream treatments selected from at least one of UV and Low rf stream plasma or thermal cure treatments in at least one of a reducing environment or inert gas ambient to enhance the reaction/intermixing between each layer and between the Cu-Metal alloy interface formed in the process.

18. The process of claim 1 wherein said electrically conductive metal alloy liner on said sidewalls comprises a multilayer metal alloy liner on said copper core.

19. The process of claim 1 for forming non-corrosive coatings for thick or large Cu substrates, comprising applying to said substrate an electrically conductive metal alloy based on Mn, with at lest one of Co and/or W where said substrate comprises metal pads used in C4 flip-chip and wire bonds, high-Q inductors, and laser-blown fuses.

9. A structure, comprising:

a wire embedded in a dielectric layer on a semiconductor substrate, said dielectric layer having a top surface said wire comprising a copper core and an electrically conductive metal alloy liner on sidewalls and a bottom of said copper core, said copper core has a top surface covered with a metal cap of said electrically conductive metal alloy liner, and wherein said electrically conductive metal alloy has a top surface and comprises an alloy of Mn with Co, Mn/Co, Co/Mn/W, W/Mn, W/Mn/Co, and combinations of Ru, Mn, and Co, wherein said alloy liner is an ultra thin liner from about 0.1 nm to less than 1.0 nm thick.

11. The structure of claim 9, wherein said top surface of said copper core and said top surface of said electrically conductive metal alloy liner are coplanar with said top surface of said dielectric layer.

12. The structure of claim 9, wherein said top surface of said electrically conductive metal alloy liner is coplanar with said top surface of said dielectric layer and said top surface of said copper core is recessed below said top surface of said dielectric layer.

13. The structure of claim 12, wherein said top surface of said copper core and said top surface of said electrically conductive metal alloy liner are coplanar with said top surface of said dielectric layer.

14. The structure of claim 9, wherein said top surface of said electrically conductive metal alloy liner is coplanar with said top surface of said dielectric layer and a top surface of said copper core is recessed below said top surface of said dielectric layer.

20. The structure of claim 9 comprising a Cu-based MEMS with Cu interconnect wiring that includes a self-aligned corrosion-resistant coating of Cu wiring.

21. The structure of claim 11 wherein said alloy liner is an ultra thin liner from about 0.1 nm to about 3.0 nm thick.

22. The structure of claim 12 wherein said alloy liner is an ultra thin liner from about 0.1 nm to about 3.0 nm thick.

24. The structure of claim 14 wherein said alloy liner is an ultra thin liner from about 0.1 nm to about 3.0 nm thick.

25. The structure of claim 9 wherein said dielectric layer extends over said metal cap.

10. (canceled)

26. The structure of claim 10 wherein said dielectric layer extends over said metal cap.

16. A deposition tool comprising:

a load/unload chamber;

a mechanism for transferring a substrate between said load/unload chamber and a deposition chamber, said deposition chamber connected to said load/unload chamber by a port; and

wherein said deposition chamber is (i) configured to selectively form a metal layer or layers on copper by chemical vapor deposition or by atomic layer deposition and (ii) is configured to form a dielectric layer by chemical vapor deposition, and additionally comprising further downstream chambers selected from at least one of a UV and a Low rf stream plasma or thermal cure means in at least one of a reducing environment ambient to enhance the reaction/intermixing between said layer or layers and said copper.

17. The deposition tool of claim 16 having from about 4 to about 5 chambers including a lower chamber, said chambers being employed for depositing multilayer metals, metal alloys and dielectrics and for optionally performing a cure treatment in said lower chamber.

23. The structure of daim 13 wherein said alloy liner is an ultra thin liner from about 0.1 nm to about 3.0 nm thick.

27. A structure, comprising:

a wire embedded in a dielectric layer on a semiconductor substrate, said dielectric layer having a top surface said wire comprising a copper core and an electrically conductive metal alloy liner on sidewalls and a bottom of said copper core, said copper core has a top surface covered with a metal cap of said electrically conductive metal alloy liner, and wherein said electrically conductive metal alloy has a top surface and comprises an alloy of Co/Mn/W, W/Mn, W/Mn/Co, and combinations of Ru, Mn, and Co.

28. The structure of claim 27 wherein said alloy liner is an ultra thin liner from about 0.1 nm to less than 1.0 nm thick.

29. The structure of claim 27, wherein said top surface of said copper core and said top surface of said electrically conductive metal alloy liner are coplanar with said top surface of said dielectric layer.

30. The structure of claim 27, wherein said top surface of said electrically conductive metal alloy liner is coplanar with said top surface of said dielectric layer and said top surface of said copper core is recessed below said top surface of said dielectric layer.

31. The structure of claim 30 wherein said top surface of said copper core and said top surface of said electrically conductive metal alloy liner are coplanar with said top surface of said dielectric layer.

32. The structure of claim 27, wherein said top surface of said electrically conductive metal alloy liner is coplanar with said top surface of said dielectric layer and a top surface of said copper core is recessed below said top surface of said dielectric layer.