INTEGRATED CIRCUIT PACKAGE HAVING WIREBONDED MULTI-DIE STACK

• US 20160276311A1
• Filed: 08/26/2014
• Published: 09/22/2016
• Est. Priority Date: 09/26/2014
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Patten, Richard, Meyer, Thorsten, Jaervinen, Pauli
• Granted Patent: US 9,972,601 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45139 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48106 the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48228 the bond pad being disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/48235 connecting the wire to a via metallisation of the item
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/85444 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/85455 : Nickel (Ni) as principal constituent
• CPC Class Codes: H01L 2224/92247 : the second connecting process involving a wire connector
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06548 : Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06575 : Auxiliary carrier between devices, the carrier having no electrical connection structure
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3135 : Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49 : wire-like arrangements or pins or rods using optical fibres H01L23/48; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/528 : Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/07 : the devices being of a type provided for in group H01L29/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1579 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.

Claims

1. An integrated circuit (IC) package comprising:

a first die at least partially embedded in a first encapsulation layer, the first die having a first plurality of die-level interconnect structures that are disposed at a first side of the first encapsulation layer;

a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between the first side of the first encapsulation layer and a second side of the first encapsulation layer that is disposed opposite to the first side; and

a second die disposed on the second side of the first encapsulation layer and at least partially embedded in a second encapsulation layer, the second die having a second plurality of die-level interconnect structures, wherein the second plurality of die-level interconnect structures are electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.

2. The IC package of claim 1, further comprising:

one or more redistribution layers (RDLs) disposed on the first side of the first encapsulation layer, wherein the one or more RDLs are electrically coupled with the first die, and wherein the one or more RDLs are electrically coupled with the second die via the plurality of electrical routing features.

3. The IC package of claim 2, further comprising a plurality of package-level interconnect structures disposed on the one or more RDLs.

4. The IC package of claim 2, further comprising a third die disposed on the one or more RDLs and having a third plurality of die-level interconnect structures electrically coupled with the one or more RDLs.

5. The IC package of claim 4, further comprising a plurality of package-level interconnect structures disposed on the one or more RDLs, wherein a combined thickness of the third die and the third plurality of die-level interconnect structures is less than a thickness of the individual package-level interconnect structures of the plurality of package-level interconnects to enable the placement of the third die in a same plane as the plurality of package-level interconnect structures.

6. The IC package of claim 1, wherein the subset of the plurality of electrical routing features is a first subset, the IC package further comprising:

a third die at least partially embedded in the second encapsulation layer and having a third plurality of die-level interconnect structures electrically coupled, by bonding wires, with a second subset of the plurality of the electrical routing features, wherein the third die and the second die are coupled together via a spacer.

7. The IC package of claim 1, wherein the plurality of electrical routing features comprise via bars.

8. The IC package of claim 1, wherein the IC package is an embedded wafer level ball grid array (eWLB) package.

9. A method of forming an integrated circuit (IC) package comprising:

providing a first encapsulation layer having a first die and a plurality of electrical routing features at least partially embedded therein, the first die having a first plurality of die-level interconnect structures that are disposed at a first side of the first encapsulation layer, wherein the electrical routing features electrically couple the first side of the first encapsulation layer with a second side of the first encapsulation layer, and wherein the first side of the first encapsulation layer is disposed opposite the second side of the first encapsulation layer;

coupling a second die with a second side of the first encapsulation layer, wherein the second die includes a second plurality of die-level interconnect structures;

electrically coupling the second plurality of die-level interconnect structures with at least a subset of the plurality of electrical routing features by bonding wires; and

forming a second encapsulation layer over the second die and the wire-bonding configuration to encapsulate at least a portion of the second die and the wire-bonding configuration in the second encapsulation layer.

10. The method of claim 9, wherein providing the first encapsulation layer comprises:

coupling the first die with a carrier;

coupling the plurality of electrical routing features with the carrier; and

depositing an encapsulation material over the first die and the plurality of electrical routing features to form the first encapsulation layer.

11. The method of claim 9, wherein providing the first encapsulation layer comprises:

coupling the first die with a carrier;

depositing an encapsulation material over the first die to form the first encapsulation layer; and

forming the plurality of electrical routing features in the encapsulation material.

12. The method of claim 9, further comprising:

forming one or more redistribution layers (RDLs) on the first side of the first encapsulation layer, wherein the one or more RDLs are electrically coupled with the first die, and wherein the one or more RDLs are electrically coupled with the second die by the plurality of electrical routing features.

13. The method of claim 12, further comprising:

forming a plurality of package-level interconnects on the one or more RDLs.

14. The method of claim 12, further comprising:

electrically coupling a third die to the one or more RDLs via a third plurality of die-level interconnect structures disposed on the third die.

15. The method of claim 14, further comprising forming a plurality of package-level interconnect structures on the one or more RDLs, wherein a combined thickness of the third die and the third plurality of die-level interconnect structures is less than a thickness of the individual package-level interconnect structures of the plurality of package-level interconnects to enable the placement of the third die in a same plane as the plurality of package-level interconnect structures.

16. The method of claim 9, wherein the subset of the plurality of electrical routing features is a first subset and the bonding wires are first bonding wires, the IC package further comprising:

physically coupling a third die having a third plurality of die-level interconnect structures to a surface of the second die via a spacer; and

electrically coupling the third plurality of die-level interconnect structures with a second subset of the plurality of electrical routing features by second bonding wires, wherein the second encapsulation layer is formed to encapsulate the third die and the

17. The method of claim 9, wherein the plurality of electrical routing features comprise via bars.

18. The method of claim 9, wherein the IC package is an embedded wafer level ball grid array (eWLB) package.

19. An integrated circuit (IC) assembly comprising:

an IC package including;

a first die at least partially embedded in a first encapsulation layer, the first die having a first plurality of die-level interconnect structures that are disposed at a first side of the first encapsulation layer;

a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between the first side of the first encapsulation layer and a second side of the first encapsulation layer that is disposed opposite to the first side;

a second die disposed on the second side of the first encapsulation layer and at least partially embedded in a second encapsulation layer, the second die having a second plurality of die-level interconnect structures, wherein the second plurality of die-level interconnect structures are electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires; and

a plurality of package-level interconnects disposed on the first side of the first encapsulation layer and electrically coupled with the second plurality of die-level interconnect structures, via the plurality of electrical routing features, and the first plurality of die-level interconnect structures; and

a circuit board having a plurality of electrical routing features disposed therein and a plurality of pads disposed thereon, wherein the plurality of pads are electrically coupled with the plurality of package-level interconnect structures.

20. The IC assembly of claim 19, wherein the IC package includes a processor.

21. The IC assembly of claim 20, further comprising one or more of an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, or a camera coupled with the circuit board.

22. The IC assembly of claim 19, wherein the IC assembly is part of a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.