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HIGH THERMAL BUDGET MAGNETIC MEMORY

  • US 20160276407A1
  • Filed: 03/15/2016
  • Published: 09/22/2016
  • Est. Priority Date: 03/16/2015
  • Status: Active Grant
First Claim
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1. A method of forming a memory cell comprising:

  • forming a select unit on a substrate, wherein the select unit comprises a transistor havinga first source/drain (S/D) region,a second S/D region, anda gate between the first and second S/D regions;

    forming a dielectric layer on the substrate covering the select unit, wherein the dielectric layer includes storage pad coupled to the first S/D region;

    forming a storage unit on the storage pad, wherein forming the storage unit comprisesforming a bottom electrode,forming a fixed layer on the bottom electrode, wherein the fixed layer comprisesa composite spacer layer disposed on the bottom electrode, wherein the composite spacer layer comprisesa base layer, andan amorphous buffer layer disposed over the base layer, anda reference layer on the composite spacer layer, wherein the amorphous buffer layer serves as a template for the reference layer to have a desired crystalline structure in a desired orientation,forming at least one tunneling barrier layer over the fixed layer,forming a storage layer over the tunneling barrier layer, andforming a top electrode over the storage layer; and

    forming a bitline coupled to the top electrode layer.

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