HIGH THERMAL BUDGET MAGNETIC MEMORY
First Claim
1. A method of forming a memory cell comprising:
- forming a select unit on a substrate, wherein the select unit comprises a transistor havinga first source/drain (S/D) region,a second S/D region, anda gate between the first and second S/D regions;
forming a dielectric layer on the substrate covering the select unit, wherein the dielectric layer includes storage pad coupled to the first S/D region;
forming a storage unit on the storage pad, wherein forming the storage unit comprisesforming a bottom electrode,forming a fixed layer on the bottom electrode, wherein the fixed layer comprisesa composite spacer layer disposed on the bottom electrode, wherein the composite spacer layer comprisesa base layer, andan amorphous buffer layer disposed over the base layer, anda reference layer on the composite spacer layer, wherein the amorphous buffer layer serves as a template for the reference layer to have a desired crystalline structure in a desired orientation,forming at least one tunneling barrier layer over the fixed layer,forming a storage layer over the tunneling barrier layer, andforming a top electrode over the storage layer; and
forming a bitline coupled to the top electrode layer.
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Accused Products
Abstract
Semiconductor devices and methods for forming a semiconductor device are disclosed. The method includes forming a storage unit of a magnetic memory cell. A bottom electrode and a fixed layer are formed. The fixed layer includes a composite spacer layer disposed on the bottom electrode. The composite spacer layer includes a base layer and an amorphous buffer layer disposed over the base layer. A reference layer is disposed on the composite spacer layer. The amorphous buffer layer serves as a template for the reference layer to have a desired crystalline structure in a desired orientation. At least one tunneling barrier layer is formed over the fixed layer. A storage layer is formed over the tunneling barrier layer and a top electrode is formed over the storage layer.
6 Citations
20 Claims
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1. A method of forming a memory cell comprising:
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forming a select unit on a substrate, wherein the select unit comprises a transistor having a first source/drain (S/D) region, a second S/D region, and a gate between the first and second S/D regions; forming a dielectric layer on the substrate covering the select unit, wherein the dielectric layer includes storage pad coupled to the first S/D region; forming a storage unit on the storage pad, wherein forming the storage unit comprises forming a bottom electrode, forming a fixed layer on the bottom electrode, wherein the fixed layer comprises a composite spacer layer disposed on the bottom electrode, wherein the composite spacer layer comprises a base layer, and an amorphous buffer layer disposed over the base layer, and a reference layer on the composite spacer layer, wherein the amorphous buffer layer serves as a template for the reference layer to have a desired crystalline structure in a desired orientation, forming at least one tunneling barrier layer over the fixed layer, forming a storage layer over the tunneling barrier layer, and forming a top electrode over the storage layer; and forming a bitline coupled to the top electrode layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method of forming a storage unit of a magnetic memory cell comprising:
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forming a bottom electrode; forming a fixed layer on the bottom electrode, wherein the fixed layer comprises a composite spacer layer disposed on the bottom electrode, wherein the composite spacer layer comprises a base layer, and an amorphous buffer layer disposed over the base layer, and a reference layer on the composite spacer layer, wherein the amorphous buffer layer serves as a template for the reference layer to have a desired crystalline structure in a desired orientation; forming at least one tunneling barrier layer over the fixed layer; forming a storage layer over the tunneling barrier layer; and forming a top electrode over the storage layer. - View Dependent Claims (13, 14, 15, 16, 17)
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18. A storage unit of a magnetic memory cell comprising:
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a bottom electrode; a fixed layer disposed on the bottom electrode, wherein the fixed layer comprises a composite spacer layer disposed on the bottom electrode, wherein the composite spacer layer comprises a base layer, and an amorphous buffer layer disposed over the base layer, and a reference layer on the composite spacer layer, wherein the amorphous buffer layer serves as a template for the reference layer to have a desired crystalline structure in a desired orientation; at least one tunneling barrier layer disposed over the fixed layer; a storage layer disposed over the tunneling barrier layer; and a top electrode disposed over the storage layer. - View Dependent Claims (19, 20)
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Specification