COMMUNICATION APPARATUS, COMMUNICATION SYSTEM, AND COMMUNICATION METHOD

• US 20160277037A1
• Filed: 09/08/2015
• Published: 09/22/2016
• Est. Priority Date: 03/16/2015
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: KAJIHARA, Hirotsugu
• Application Number:
  US14/848,287
• Publication Number:
  US 20160277037A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03M 13/1102 Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
• CPC Class Codes: H03M 13/23 using convolutional codes, e.g. unit memory codes
• CPC Class Codes: H03M 13/2757 Interleaver with an interleaving rule not provided for in the subgroups H03M13/2703 - H03M13/2753
• CPC Class Codes: H03M 13/2792 Interleaver wherein interleaving is performed jointly with another technique such as puncturing, multiplexing or routing
• CPC Class Codes: H03M 13/35 Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27

Abstract

A communication apparatus includes a deinterleaver and an error corrector. The deinterleaver sets, as an input, a third error-correction-code sequence obtained by rearranging bit positions of a second error-correction-code sequence in which two or more terminated first error-correction-code sequences are repeated from the terminated first error-correction-code sequences in accordance with a first rule. The deinterleaver rearranges bit positions of the third error-correction-code sequence in accordance with a second rule that is different from the first rule to configure a fourth error-correction-code sequence including one or more of the terminated first error-correction-code sequences. The error corrector performs error correction based on the fourth error-correction-code sequence. The second rule used by the deinterleaver is to extract bits capable of configuring the fourth error-correction-code sequence in order from a head of the third error-correction-code sequence.

Claims

1. A communication apparatus comprising:

a deinterleaver setting, as an input, a third error-correction-code sequence obtained by rearranging bit positions of a second error-correction-code sequence in which two or more terminated first error-correction-code sequences are repeated from the terminated first error-correction-code sequences in accordance with a first rule, and rearranging bit positions of an input third error-correction-code sequence in accordance with a second rule that is different from the first rule to configure a fourth error-correction-code sequence including one or more of the terminated first error-correction-code sequences; and

an error corrector that performs error correction based on the fourth error-correction-code sequence, wherein

the second rule used by the deinterleaver is to extract bits capable of configuring the fourth error-correction-code sequence in order from a head of the third error-correction-code sequence.

2. The apparatus of claim 1, wherein the bits capable of configuring the fourth error-correction-code sequence include a bit group belonging to a bit string having a smallest bit number counted from the head of the third error-correction-code sequence.

3. The apparatus of claim 1, further comprising a decoder that decodes data subsequent to the third error-correction-code sequence based on the fourth error-correction-code sequence.

4. The apparatus of claim 3, wherein the deinterleaver changes number of the terminated first error-correction-code sequences to be included in the fourth error-correction-code sequence according to a time required for configuring the fourth error-correction-code sequence.

5. The apparatus of claim 3, wherein the decoder decodes the subsequent data while omitting deinterleaving.

6. The apparatus of claim 1, wherein the deinterleaver comprises information regarding the first rule, and extracts bits capable of configuring the fourth error-correction-code sequence based on the information.

7. A communication system comprising:

a transmission device; and

a reception device, wherein

the transmission device comprises an interleaver rearranging bit positions of a second error-correction-code sequence in which two or more terminated first error-correction-code sequences are repeated from the terminated first error-correction-code sequences in accordance with a first rule to configure a third error-correction-code sequence,

the reception device comprises

a deinterleaver receiving the third error-correction-code sequence as an input, and rearranging bit positions of an input third error-correction-code sequence in accordance with a second rule that is different from the first rule to configure a fourth error-correction-code sequence including one or more of the terminated first error-correction-code sequences, and

an error corrector that performs error correction based on the fourth error-correction-code sequence, and wherein

the second rule used by the deinterleaver is to extract bits capable of configuring the fourth error-correction-code sequence in order from a head of the third error-correction-code sequence.

8. The system of claim 7, wherein the bits capable of configuring the fourth error-correction-code sequence include a bit group belonging to a bit string having a smallest bit number counted from the head of the third error-correction-code sequence.

9. The system of claim 7, wherein the reception device further comprises a decoder that decodes data subsequent to the third error-correction-code sequence based on the fourth error-correction-code sequence.

10. The system of claim 9, wherein the deinterleaver changes number of the terminated first error-correction-code sequences to be included in the fourth error-correction-code sequence according to a time required for configuring the fourth error-correction-code sequence.

11. The system of claim 9, wherein the decoder decodes the subsequent data while omitting deinterleaving.

12. The system of claim 7, wherein the deinterleaver comprises information regarding the first rule, and extracts bits capable of configuring the fourth error-correction-code sequence based on the information.

13. A communication method comprising:

setting, as an input, a third error-correction-code sequence obtained by rearranging bit positions of a second error-correction-code sequence in which two or more terminated first error-correction-code sequences are repeated from the terminated first error-correction-code sequences in accordance with a first rule, and rearranging bit positions of an input third error-correction-code sequence in accordance with a second rule that is different from the first rule to configure a fourth error-correction-code sequence including one or more of the terminated first error-correction-code sequences; and

performing error correction based on the fourth error-correction-code sequence, wherein

the second rule is to extract bits capable of configuring the fourth error-correction-code sequence in order from a head of the third error-correction-code sequence.

14. The method of claim 13, wherein the bits capable of configuring the fourth error-correction-code sequence include a bit group belonging to a bit string having a smallest bit number counted from the head of the third error-correction-code sequence.

15. The method of claim 13, wherein data subsequent to the third error-correction-code sequence is decoded based on the fourth error-correction-code sequence.

16. The method of claim 15, wherein number of the terminated first error-correction-code sequences to be included in the fourth error-correction-code sequence is changed according to a time required for configuring the fourth error-correction-code sequence.

17. The method of claim 15, wherein the subsequent data is decoded while omitting deinterleaving.

18. The method of claim 13, wherein bits capable of configuring the fourth error-correction-code sequence are extracted based on information regarding the first rule.