UPDATING OF A RECIPE FOR EVALUATING A MANUFACTURING STAGE OF AN ELECTRICAL CIRCUIT

• US 20160282856A1
• Filed: 03/24/2015
• Published: 09/29/2016
• Est. Priority Date: 03/24/2015
• Status: Active Grant

• Current Assignee: Applied Materials Israel Limited (Applied Materials Incorporated)
• Original Assignee: Applied Materials Israel Limited (Applied Materials Incorporated)
• Inventors: Wachs, Amir
• Granted Patent: US 9,880,550 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G05B 19/41875 characterised by quality surveillance of production
• CPC Class Codes: G05B 2219/31443 Keep track of nc program, recipe program
• CPC Class Codes: G05B 2219/45031 Manufacturing semiconductor wafers
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

A computerized system that may include a recipe module and a yield diagnostics module. The yield diagnostics module may be configured to generate evaluation results that are indicative of an outcome of an evaluation process of at least one manufacturing stage of at least one electrical circuit. The evaluation results differ from end of line (EOL) results. The recipe module may be configured to receive EOL results relating to the at least one electrical circuit, to receive the evaluation results relating to the at least one electrical circuit; to correlate the evaluation results and the EOL results to provide correlation results; and respond to the correlation results. The responding to the correlation results may include determining whether to alter a recipe in response to the correlation results and altering the recipe if it is determined to alter the recipe.

Claims

1. A computerized system that comprises a recipe module and a yield diagnostics module:

wherein the yield diagnostics module is configured to generate evaluation results that are indicative of an outcome of an evaluation process of at least one manufacturing stage of at least one electrical circuit;

wherein the evaluation results differ from end of line (EOL) results;

wherein the recipe module is configured to receive EOL results relating to the at least one electrical circuit, to receive the evaluation results relating to the at least one electrical circuit;

to correlate the evaluation results and the EOL results to provide correlation results; and

respond to the correlation results;

wherein a responding to the correlation results comprises determining whether to alter a recipe in response to the correlation results and altering the recipe if it is determined to alter the recipe.

2. A method for evaluating a recipe, the method is executed by a computerized system and comprises:

generating or receiving evaluation results that are indicative of an outcome of an evaluation process of at least one manufacturing stage of at least one electrical circuit;

wherein the evaluation results differ from end of line (EOL) results;

receiving or generating EOL results relating to the at least one electrical circuit;

correlating the evaluation results and the EOL results to provide correlation results; and

responding to the correlation results;

wherein the responding comprises determining whether to alter the recipe in response to the correlation results and altering the recipe if it is determined to alter the recipe.

3. The method according to claim 2 wherein the correlating comprises categorizing defects to one of the following categories:

detected fault-causing defect, non-fault-causing defects and undetected fault-causing defects.

4. The method according to claim 3 comprising altering the recipe in response to the categorizing of defects.

5. The method according to claim 3 comprising altering the recipe to include an evaluation of locations that correspond to locations of undetected fault causing defects.

6. The method according to claim 3 comprising altering the recipe to include an evaluation of locations that correspond to locations of detected fault causing defect.

7. The method according to claim 3 comprising adding to the recipe of a scanning electron microscopy review of locations that correspond to locations of at least one category of defect.

8. The method according to claim 2 comprising adding to the recipe a hot spot inspection.

9. The method according to claim 2 comprising retrieving design data about the electrical circuit and evaluating the correlation results in response to the design data.

10. A non-transitory computer readable medium that stores instructions that once executed by a computerized system cause the computerized system to execute the stages of:

generating or receiving evaluation results that are indicative of an outcome of an evaluation process of at least one manufacturing stage of at least one electrical circuit;

wherein the evaluation results differ from end of line (EOL) results;

receiving or generating EOL results relating to the at least one electrical circuit;

correlating the evaluation results and the EOL results to provide correlation results; and

responding to the correlation results;

wherein the responding comprises determining whether to alter a recipe in response to the correlation results and altering the recipe if it is determined to alter the recipe.

11. The non-transitory computer readable medium according to claim 10 wherein the correlating comprises categorizing defects to one of the following categories:

detected fault-causing defect,

non-fault-causing defects, and

undetected fault-causing defects.

12. The non-transitory computer readable medium according to claim 11 that stores instructions for altering the recipe in response to the categorizing of defects.

13. The non-transitory computer readable medium according to claim 11 that stores instructions for altering the recipe to include an evaluation of locations that correspond to locations of undetected fault causing defects.

14. The non-transitory computer readable medium according to claim 11 that stores instructions for altering the recipe to include an evaluation of locations that correspond to locations of detected fault causing defect.

15. The non-transitory computer readable medium according to claim 11 that stores instructions for adding to the recipe of a scanning electron microscopy review of locations that correspond to locations of at least one category of defect.