MEMORY SYSTEM AND OPERATING METHOD THEREOF

• US 20160283138A1
• Filed: 03/25/2016
• Published: 09/29/2016
• Est. Priority Date: 03/25/2015
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Memory Solutions Incorporated (SK Hynix Inc.)
• Inventors: LEHMAN, Curtis, LIAO, Frank
• Granted Patent: US 10,180,805 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

Memory systems may include a memory device with multiple dies, a first super block, and a second super block, the first super block including a first meta-page stored at a location on a die and the second super block including a second-meta page stored at a location on a die; and a controller suitable for reading the meta-pages in the super blocks, wherein the stored location of the first meta-page is staggered with respect to the stored location of the second meta-page such that the first meta-page and the second meta-page are read by the controller during a single read.

Claims

1. A memory system comprising:

a memory device including;

multiple dies;

a first super block; and

a second super block, the first super block including a first meta-page stored at a location on a die and the second super block including a second-meta page stored at a location on a die; and

a controller suitable for reading the meta-pages in the super blocks,

wherein the stored location of the first meta-page is staggered with respect to the stored location of the second meta-page such that the first meta-page and the second meta-page are read by the controller during a single read.

2. The memory system according to claim 1, wherein the memory device includes a third super block with a third meta-page stored at a location on a die and a fourth super block with a fourth meta-page stored at a location on a die.

3. The memory system according to claim 2, wherein the stored locations of each of the meta-pages is staggered with respect to each other such that each of the meta-pages are read by the controller during a single read.

4. The memory system according to claim 1, wherein the meta-pages include information regarding corresponding super blocks used for sudden power-off recovery.

5. The memory system according to claim 4, wherein the meta-pages include information indicating whether a corresponding super block is a closed block.

6. The memory system according to claim 5, wherein the meta-pages include mapping information between logical block addresses and physical block addresses.

7. The memory system according to claim 1, wherein the controller is further suitable for updating and rebuilding logical block addressing (LBA) information for the super blocks based on the meta-pages.

8. A method comprising:

storing a first meta-page corresponding to a first super block at a location on a die;

storing a second meta-page corresponding to a second super block at a location on a die, such that the stored location of the first meta-page is staggered with respect to the stored location of the second meta-page; and

reading the first meta-page and the second meta-page during a single read.

9. The method of claim 8, further comprising:

storing a third meta-page corresponding to a third super block at a location on a die; and

storing a fourth meta-page corresponding to a fourth super block at a location on a die.

10. The method of claim 9, wherein the third meta-page and fourth meta-page are stored such that the stored locations of each meta-page is staggered with respect to each other.

11. The method of claim 10, further comprising reading the meta-pages during a single read.

12. The method of claim 8, wherein the meta-pages include information regarding corresponding super blocks used for sudden power-off recovery.

13. The method of claim 12, wherein the meta-pages include information indicating whether a corresponding super block is a closed block.

14. The method of claim 13, wherein the meta-pages include mapping information between logical block addresses and physical block addresses.

15. The method of claim 8, further comprising updating and rebuilding logical block addressing information for the super blocks based on the meta-pages.

16. A memory device, including:

multiple dies; and

a plurality of super blocks, each of the plurality of super blocks including a meta-page stored at a location on a die of the multiple dies, wherein the stored locations of each of the meta-pages is staggered with respect to each other such that each of the meta-pages are read during a single read command.