Embedded Branch Prediction Unit
First Claim
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1. A processor comprising:
- a pipeline comprising;
an instruction fetch stage having an instruction fetch unit and a branch prediction unit including;
a branch target buffer; and
a prediction history buffer, wherein the branch prediction unit is to provide an index to the instruction fetch unit to enable the instruction fetch unit to use the index to lookup the prediction history buffer;
an instruction decode stage coupled to an output of the instruction fetch stage and having an instruction decode unit and a return address stack for the instruction decode unit, the return address stack structurally separated from the branch prediction unit;
an operand fetch stage coupled to an output of the instruction decode stage; and
an execution stage coupled to an output of the operand fetch stage.
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Abstract
In accordance with some embodiments of the present invention, a branch prediction unit for an embedded controller may be placed in association with the instruction fetch unit instead of the decode stage. In addition, the branch prediction unit may include no branch predictor. Also, the return address stack may be associated with the instruction decode stage and is structurally separate from the branch prediction unit. In some cases, this arrangement reduces the area of the branch prediction unit, as well as power consumption.
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Citations
20 Claims
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1. A processor comprising:
a pipeline comprising; an instruction fetch stage having an instruction fetch unit and a branch prediction unit including; a branch target buffer; and a prediction history buffer, wherein the branch prediction unit is to provide an index to the instruction fetch unit to enable the instruction fetch unit to use the index to lookup the prediction history buffer; an instruction decode stage coupled to an output of the instruction fetch stage and having an instruction decode unit and a return address stack for the instruction decode unit, the return address stack structurally separated from the branch prediction unit; an operand fetch stage coupled to an output of the instruction decode stage; and an execution stage coupled to an output of the operand fetch stage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method comprising:
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receiving, in an instruction fetch unit of an instruction fetch stage of a processor pipeline, a misprediction signal from a branch prediction unit of the instruction fetch stage; providing an index to the instruction fetch unit to enable the instruction fetch unit to use the index to lookup a prediction history buffer of the branch prediction unit; pushing a next program counter onto a top of a return address stack for a call instruction, the return address stack included in an instruction decode stage of the processor pipeline, the instruction decode stage coupled to an output of the instruction fetch stage and including an instruction decode unit and the return address stack, the return address stack structurally separated from the branch prediction unit; and popping a first entry of the return address stack for a return instruction decoded in the instruction decode unit. - View Dependent Claims (12, 13, 14, 15, 16)
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17. A non-transitory computer readable medium storing instructions to enable a processor to perform a method comprising:
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receiving, in an instruction fetch unit of an instruction fetch stage of a processor pipeline, a misprediction signal from a branch prediction unit of the instruction fetch stage; providing an index to the instruction fetch unit to enable the instruction fetch unit to use the index to lookup a prediction history buffer of the branch prediction unit; pushing a next program counter onto a top of a return address stack for a call instruction, the return address stack included in an instruction decode stage of the processor pipeline, the instruction decode stage coupled to an output of the instruction fetch stage and including an instruction decode unit and the return address stack, the return address stack structurally separated from the branch prediction unit; and popping a first entry of the return address stack for a return instruction decoded in the instruction decode unit. - View Dependent Claims (18, 19, 20)
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Specification