Embedded Branch Prediction Unit

• US 20160283244A1
• Filed: 06/07/2016
• Published: 09/29/2016
• Est. Priority Date: 12/30/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Jiang, Xiaowei, Makineni, Srihari, Fang, Zhen, Pavlov, Dmitri, Iyer, Ravi
• Granted Patent: US 9,753,732 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 9/30054 Unconditional branch instructions
• CPC Class Codes: G06F 9/30058 Conditional branch instructions
• CPC Class Codes: G06F 9/3806 using address prediction, e.g. return stack, branch history buffer

Abstract

In accordance with some embodiments of the present invention, a branch prediction unit for an embedded controller may be placed in association with the instruction fetch unit instead of the decode stage. In addition, the branch prediction unit may include no branch predictor. Also, the return address stack may be associated with the instruction decode stage and is structurally separate from the branch prediction unit. In some cases, this arrangement reduces the area of the branch prediction unit, as well as power consumption.

Claims

1. A processor comprising:

a pipeline comprising;

an instruction fetch stage having an instruction fetch unit and a branch prediction unit including;

a branch target buffer; and

a prediction history buffer, wherein the branch prediction unit is to provide an index to the instruction fetch unit to enable the instruction fetch unit to use the index to lookup the prediction history buffer;

an instruction decode stage coupled to an output of the instruction fetch stage and having an instruction decode unit and a return address stack for the instruction decode unit, the return address stack structurally separated from the branch prediction unit;

an operand fetch stage coupled to an output of the instruction decode stage; and

an execution stage coupled to an output of the operand fetch stage.

2. The processor of claim 1, wherein the branch target buffer has a plurality of entries to store a tag, a target address and last byte information.

3. The processor of claim 2, wherein the prediction history buffer has a plurality of entries to store a branch identifier, last byte information, and a target address.

4. The processor of claim 2, wherein the branch target buffer is to update only branches that are taken, and indirect branches are not to be sent to the branch prediction unit for update.

5. The processor of claim 1, wherein the instruction decode unit is to push a next program counter onto a top of the return address stack for a call instruction.

6. The processor of claim 1, wherein the processor comprises an embedded controller comprising an in order processor.

7. The processor of claim 1, wherein the branch prediction unit does not include a branch predictor.

8. The processor of claim 1, further comprising a write back stage coupled to an output of the execution stage.

9. The processor of claim 1, wherein the instruction decode unit is to pop a first entry of the return address stack for a return instruction, and the branch prediction unit is to send a target back to the instruction fetch stage for an immediate fix in the same cycle.

10. The processor of claim 1, wherein the branch prediction unit includes:

a prediction interface;

a next instruction pointer interface; and

an update interface.

11. A method comprising:

receiving, in an instruction fetch unit of an instruction fetch stage of a processor pipeline, a misprediction signal from a branch prediction unit of the instruction fetch stage;

providing an index to the instruction fetch unit to enable the instruction fetch unit to use the index to lookup a prediction history buffer of the branch prediction unit;

pushing a next program counter onto a top of a return address stack for a call instruction, the return address stack included in an instruction decode stage of the processor pipeline, the instruction decode stage coupled to an output of the instruction fetch stage and including an instruction decode unit and the return address stack, the return address stack structurally separated from the branch prediction unit; and

popping a first entry of the return address stack for a return instruction decoded in the instruction decode unit.

12. The method of claim 11, further comprising storing a tag, a target address and last byte information in a branch target buffer of the branch prediction unit.

13. The method of claim 12, further comprising storing a branch identifier, last byte information, and a target address in the prediction history buffer of the branch prediction unit.

14. The method of claim 12, further comprising updating in the branch target buffer only branches that are taken.

15. The method of claim 14, further comprising not sending indirect branches to the branch prediction unit for update.

16. The method of claim 11, further comprising sending a target back to the instruction fetch stage for an immediate fix in the same cycle.

17. A non-transitory computer readable medium storing instructions to enable a processor to perform a method comprising:

receiving, in an instruction fetch unit of an instruction fetch stage of a processor pipeline, a misprediction signal from a branch prediction unit of the instruction fetch stage;

providing an index to the instruction fetch unit to enable the instruction fetch unit to use the index to lookup a prediction history buffer of the branch prediction unit;

pushing a next program counter onto a top of a return address stack for a call instruction, the return address stack included in an instruction decode stage of the processor pipeline, the instruction decode stage coupled to an output of the instruction fetch stage and including an instruction decode unit and the return address stack, the return address stack structurally separated from the branch prediction unit; and

popping a first entry of the return address stack for a return instruction decoded in the instruction decode unit.

18. The non-transitory computer readable medium of claim 17, further comprising instructions that when executed enable the processor to store a tag, a target address and last byte information in a branch target buffer of the branch prediction unit.

19. The non-transitory computer readable medium of claim 18, further comprising instructions that when executed enable the processor to store a branch identifier, last byte information, and a target address in the prediction history buffer of the branch prediction unit.

20. The non-transitory computer readable medium of claim 17, further comprising instructions that when executed enable the processor to send a target back to the instruction fetch stage for an immediate fix in the same cycle.