MEMORY SYSTEM WITH ROBUST BACKUP AND RESTART FEATURES AND REMOVABLE MODULES

• US 20160283327A1
• Filed: 06/06/2016
• Published: 09/29/2016
• Est. Priority Date: 08/11/2009
• Status: Active Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: FROST, Holloway H., DAVIS, Don D., GLOVER, Adrian P., SHELTON, Lance W.
• Application Number:
  US15/175,003
• Publication Number:
  US 20160283327A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/28 Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24
• CPC Class Codes: G06F 11/07 Responding to the occurrence of a fault, e.g. fault tolerance
• CPC Class Codes: G06F 11/1451 by selection of backup contents
• CPC Class Codes: G06F 11/1469 Backup restoration techniques
• CPC Class Codes: G06F 11/2015 Redundant power supplies power supply failure G06F1/30
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 2201/805 Real-time
• CPC Class Codes: G06F 2201/85 Active fault masking without idle spares active fault masking without idle spare hardware where processing functionality is redundant G06F11/2035
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory

Abstract

A Flash-based memory system comprises a plurality of Flash memory devices, a Flash controller communicating independently with each Flash memory device to perform memory operations, a power circuit providing power the Flash memory devices, and a CPU configured to perform a controlled powering down procedure upon detecting a power failure. In some embodiments, the Flash-based memory system includes a backup power source having a charge storage device and charging circuitry, the CPU configured to perform one or more test procedures on the charge storage device to provide an indication of a charge storage capacity of the charge storage device. A plurality of Flash-based memory systems may be mounted on a Flash-based memory card, and multiple such Flash-based memory cards may be combined into a Flash-based memory module. A number of Flash-based memory modules may then be removably mounted in a rack-mountable housing to form unitary Flash-based memory unit.

Claims

1. A method of backing up and recovering data in a nonvolatile memory system, comprising:

performing memory operations on a plurality of nonvolatile memory devices in the nonvolatile memory system, each nonvolatile memory device having a physical memory space that is divided into blocks, each block being further divided into pages, each page representing an individually addressable memory location on which memory operations are performed, multiple memory locations being erased at the same time in one-block groupings;

accessing a logical-to-physical translation table that associates a logical address of a memory operation with a physical address of a memory location;

detecting a power failure in the nonvolatile memory system;

performing a controlled powering down procedure upon detecting the power failure, the controlled powering down procedure comprising;

determining whether the nonvolatile memory system was in normal operation when the power failure is detected;

removing power from the nonvolatile memory devices without backing up data upon determining that the nonvolatile memory system was not in normal operation when the power failure is detected; and

removing power from the nonvolatile memory devices after backing up selected data upon determining that the nonvolatile memory system was in normal operation when the power failure is detected, wherein the backing up of selected data comprises;

storing the logical-to-physical translation table in predefined memory locations in the nonvolatile memory devices; and

storing system data in a nonvolatile backup memory of a central processing unit, the system data including data reflecting bad blocks within the nonvolatile memory devices, a pointer pointing to the predefined memory locations in the nonvolatile memory devices where the logical-to-physical translation table is stored, and error correction information associated with the system data.

2. The method according to claim 1, wherein the backing up of selected data further comprises one or more of the following:

i) blocking further access to the nonvolatile memory devices from external devices;

ii) allowing memory operations already underway when the power failure is detected to be completed; and

iii) disabling further logical-to-physical translations of logical addresses to physical addresses.

3. The method according to claim 1, wherein the CPU also has or is connected to a volatile memory and the backing up of selected data further comprises storing data from the volatile memory of the CPU to predetermined memory locations in the nonvolatile memory devices.

4. The method according to claim 1, wherein the controlled powering down procedure further comprises aborting any nonvolatile memory operations that were about to be issued when the power failure is detected.

5. The method according to claim 1, wherein the controlled powering down procedure comprises removing power from the nonvolatile memory devices and the CPU in a predefined sequence.

6. The method according to claim 1, further comprising:

determining that the controlled powering down procedure has been performed;

restoring the system data from the nonvolatile backup memory of the CPU; and

using the system data restored from the nonvolatile backup memory of the CPU to restore the logical-to-physical translation table from the predefined memory locations in the nonvolatile memory devices.

7. The method according to claim 6, wherein the nonvolatile memory system includes a field programmable device, further comprising programming the field programmable device with a first set of instructions for performing data recovery operations, and a second set of instructions for performing normal memory operations.

8. A method of backing up and recovering data in a nonvolatile memory module, comprising:

receiving communication from a plurality of input/output (I/O) modules, each I/O module configured to communicate with an external device over one or more external communication links, one or more of the I/O modules connected to and in communication with a cross-bar switching element; and

performing memory operations on a plurality of nonvolatile memory cards connected to and in communication with each crossbar switching element, each nonvolatile memory card having a printed circuit board (PCB) and a plurality of nonvolatile memory systems mounted on the PCB, each nonvolatile memory system comprising a plurality of nonvolatile memory devices, each nonvolatile memory device having a physical memory space that is divided into blocks, each block being further divided into pages, each page representing an individually addressable memory location on which memory operations are performed, multiple memory locations being erased at the same time in one-block groupings;

accessing a logical-to-physical translation table that associates a logical address of a memory operation with a physical address of a memory location;

providing primary power to at least the plurality of nonvolatile memory devices; and

upon detecting failure of the primary power;

providing backup power to at least the plurality of nonvolatile memory devices; and

performing a data backup procedure on selected data in the nonvolatile memory system and a controlled powering down procedure on the nonvolatile memory devices.

9. The method according to claim 8, wherein backing up selected data for each nonvolatile memory system comprises:

storing the logical-to-physical translation table for the nonvolatile memory system at predefined memory locations in the nonvolatile memory devices of the nonvolatile memory system; and

storing system data in a non-volatile backup memory of a CPU for the nonvolatile memory system, the system data including data reflecting bad blocks within the nonvolatile memory devices of the nonvolatile memory system, a pointer pointing to the predefined memory locations in the nonvolatile memory devices where the logical-to-physical translation table is stored, and error correction information associated with the system data.

10. The method according to claim 8, further comprising allowing individual nonvolatile memory cards to be powered down and removed from the nonvolatile memory module without powering down the nonvolatile memory module.

11. The method according to claim 8, further comprising transferring data or information to and from a central system controller, wherein each cross-bar switching element is coupled to receive commands and control signals from the central system controller.

12. The method according to claim 8, further comprising housing the nonvolatile memory cards a box-like housing, the box-like structure having a motherboard mounted therein that is configured to receive the nonvolatile memory cards.

13. The method according to claim 12, wherein a plurality of the box-like structures are removably mounted in a rack-mountable housing, each box-like structure containing a nonvolatile memory module therein.