FAIL-SAFE WRITE BACK CACHING MODE DEVICE DRIVER FOR NON VOLATILE STORAGE DEVICE

• US 20160283385A1
• Filed: 03/27/2015
• Published: 09/29/2016
• Est. Priority Date: 03/27/2015
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Boyd, James A., Trika, Sanjeev N., Juenemann, Dale J.
• Application Number:
  US14/671,871
• Publication Number:
  US 20160283385A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/205 Hybrid memory, e.g. using both volatile and non-volatile memory
• CPC Class Codes: G06F 2212/222 Non-volatile memory
• CPC Class Codes: G06F 2212/603 of operating mode, e.g. cache mode or local memory mode
• CPC Class Codes: G06F 9/4411 Configuring for operating with peripheral devices; Loading of device drivers
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method is described that includes performing the following by a device driver of a non volatile storage device: caching information targeted for the storage device into a non volatile region of a system memory without writing the information through into the storage device.

Claims

1. A method, comprising:

performing the following by a device driver of a non volatile storage device;

caching information targeted for said storage device into a non volatile region of a system memory without writing said information through into said storage device.

2. The method of claim 1 further comprising leaving said information within said non volatile region of system memory and not transferring said information from said non volatile region of system memory to said storage device as part of a power down cycle of a computing system having said device driver and said storage device.

3. The method of claim 1 wherein said device driver is a filter driver.

4. The method of claim 1 wherein said device driver accesses said storage device without communicating with a lower separable device driver.

5. The method of claim 1 wherein said system memory is a multi-level system memory.

6. The method of claim 1 wherein said non volatile region of system memory is composed of any of:

a phase change memory;

a ferro-electric memory;

a magnetic memory;

a spin transfer torque memory;

a resistor memory;

a Memristor memory.

7. The method of claim 1 wherein said method further comprises informing a user that said storage device is operating in a power-fail-safe mode.

8. The method of claim 1 further comprising permitting a user to over-ride a default write-back caching mode in favor of a write-through mode.

9. A computer readable storage medium having stored thereon device driver program code for a non volatile storage device that when processed by one or more processors of a computing system causes a method to be performed, the method comprising:

caching information targeted for said storage device into a non volatile region of a system memory without writing the information through into said storage device.

10. The computer readable storage medium of claim 9 further comprising leaving said information within said non volatile region of system memory and not transferring said information from said non volatile region of system memory to said storage device as part of a power down cycle of a computing system having said device driver and said storage device.

11. The computer readable storage medium of claim 9 wherein said device driver is a filter driver.

12. The computer readable storage medium of claim 9 wherein said device driver accesses said storage device without communicating with a lower, separable device driver.

13. The computer readable storage medium of claim 9 wherein said system memory is a multi-level system memory.

14. The computer readable storage medium of claim 9 wherein said non volatile region of system memory is composed of any of:

a phase change memory;

a ferro-electric memory;

a magnetic memory;

a spin transfer torque memory;

a resistor memory;

an Memristor memory.

15. The computer readable storage medium of claim 9 wherein said method further comprises informing a user that said storage device is operating in a power-fail-safe mode.

16. The computer readable storage medium of claim 9 further comprising permitting a user to over-ride a default write-back caching mode in favor of a write-through mode.

17. A computing system, comprising:

a) one or more processors coupled to a memory controller;

b) a multi-level system memory coupled to said memory controller, said multi-level system memory comprising a non volatile system memory region;

c) a computer readable storage medium having stored thereon device driver program code for a non volatile storage device of said computing system that when processed by the one or more processors of said computing system causes a method to be performed, the method comprising;

caching information targeted for said storage device into said non volatile region of a system memory without writing the information through into the storage device.

18. The computer system of claim 17 further comprising leaving said information within said non volatile region of system memory and not transferring said information from said non volatile region of system memory to said storage device as part of a power down cycle of a computing system having said device driver and said storage device.

19. The computer system of claim 18 wherein said device driver is a filter driver.

20. The computer system of claim 17 wherein said device driver accesses said storage device without communicating with a lower, separable device driver.

21. The computer system of claim 17 wherein said system memory is a multi-level system memory.

22. The computer system of claim 17 wherein said non volatile region of system memory is composed of any of:

a phase change memory;

a ferro-electric memory;

a magnetic memory;

a spin transfer torque memory;

a resistor memory;

an Memristor memory.

23. The computer system of claim 17 wherein said method further comprises informing a user that said storage device is operating in a power-fail-safe mode.

24. The computer system of claim 17 further comprising permitting a user to over-ride a default write-back caching mode in favor of a write-through mode.