APPARATUS, SYSTEM AND METHOD FOR SHARING PHYSICAL LAYER LOGIC ACROSS MULTIPLE PROTOCOLS
First Claim
1. An integrated circuit comprising:
- first circuitry including;
a first state machine configured to transition among first states based on both a request for power and a request for a first clock signal each on behalf of a first port controller, the first state machine further to generate a first control signal;
a second state machine configured to transition among second states based on a request for a second clock signal on behalf of the first port controller, wherein a first frequency of the first clock signal is greater than a second frequency of the second clock signal, the second state machine further to generate a second control signal; and
first clock control logic responsive to the first control signal to transmit the first clock signal toward the first port controller, and further responsive to the second control signal to transmit the second clock signal toward the first port controller; and
a third state machine configured to transition among third states based on requests from the first state machine and the second state machine, the third state machine to send from the first circuitry to physical layer circuitry requests on behalf of the first port controller.
1 Assignment
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Accused Products
Abstract
Techniques and mechanisms to provide common interface logic for multiple protocol engines to access physical layer circuitry at different times. In an embodiment, a state machine of an interface device is to participate in exchanges with physical layer resources on behalf of any of various protocol engines coupled to the interface device via different respective interfaces. Based on state transitions by the state machine, circuitry corresponding to a particular one of such interfaces may selectively send a clock signal for operation of a port controller attempting to access the physical layer circuitry. In some embodiments, multiple interface devices are configured to provide an hierarchical interface architecture for more than two port controllers that variously support at least two protocols.
7 Citations
23 Claims
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1. An integrated circuit comprising:
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first circuitry including; a first state machine configured to transition among first states based on both a request for power and a request for a first clock signal each on behalf of a first port controller, the first state machine further to generate a first control signal; a second state machine configured to transition among second states based on a request for a second clock signal on behalf of the first port controller, wherein a first frequency of the first clock signal is greater than a second frequency of the second clock signal, the second state machine further to generate a second control signal; and first clock control logic responsive to the first control signal to transmit the first clock signal toward the first port controller, and further responsive to the second control signal to transmit the second clock signal toward the first port controller; and a third state machine configured to transition among third states based on requests from the first state machine and the second state machine, the third state machine to send from the first circuitry to physical layer circuitry requests on behalf of the first port controller. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method at an integrated circuit, the method comprising:
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transitioning a first state machine of first circuitry among first states based on both a request for power and a request for a first clock signal each on behalf of a first port controller; transitioning a second state machine of the first circuitry among second states based on a request for a second clock signal on behalf of the first port controller, wherein a first frequency of the first clock signal is greater than a second frequency of the second clock signal; in response to a first control signal from the first state machine, transmitting the first clock signal from first clock control logic of the first circuitry toward the first port controller; in response to a second control signal from the second state machine, transmitting the second clock signal from the first clock control logic of the first circuitry toward the first port controller; transitioning a third state machine of the first circuitry among third states based on requests from the first state machine and the second state machine; and sending requests on behalf of the first port controller from the third state machine to physical layer circuitry. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. A system comprising
an integrated circuit including: -
first circuitry comprising; a first state machine configured to transition among first states based on both a request for power and a request for a first clock signal each on behalf of a first port controller, the first state machine further to generate a first control signal; a second state machine configured to transition among second states based on a request for a second clock signal on behalf of the first port controller, wherein a first frequency of the first clock signal is greater than a second frequency of the second clock signal, the second state machine further to generate a second control signal; and first clock control logic responsive to the first control signal to transmit the first clock signal toward the first port controller, and further responsive to the second control signal to transmit the second clock signal toward the first port controller; and a third state machine configured to transition among third states based on requests from the first state machine and the second state machine, the third state machine to send from the first circuitry to physical layer circuitry requests on behalf of the first port controller; and a touchscreen to present a display based on an exchange via the first port controller. - View Dependent Claims (19, 20, 21, 22, 23)
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Specification