COST OPTIMIZED SINGLE LEVEL CELL MODE NON-VOLATILE MEMORY FOR MULTIPLE LEVEL CELL MODE NON-VOLATILE MEMORY

• US 20160284393A1
• Filed: 03/27/2015
• Published: 09/29/2016
• Est. Priority Date: 03/27/2015
• Status: Active Grant

• Current Assignee: SK Hynix NAND Product Solutions Corporation (SK Hynix Inc.)
• Original Assignee: Intel Corporation
• Inventors: Ramalingam, Anand S.
• Granted Patent: US 10,008,250 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0035 Evaluating degradation, retention or wearout, e.g. by counting writing cycles
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 2213/71 Three dimensional array

Abstract

Methods and apparatus related to cost optimized Single Level Cell (SLC) write buffering for Three Level Cell (TLC) Solid State Drives (SSDs) are described. In one embodiment, non-volatile memory includes a first region in a Single Level Cell (SLC) mode and a second region in a multiple level cell mode. A portion of the second region is moved from the multiple level cell mode to the SLC mode, without adding any new capacity to the non-volatile memory and without reducing any existing capacity from the non-volatile memory. Other embodiments are also disclosed and claimed.

Claims

1. An apparatus comprising:

non-volatile memory to include a first region in a Single Level Cell (SLC) mode a second region in a multiple level cell (MLC) mode, and a third region in the MLC mode, wherein the third region is to be unexposed as user addressable space; and

logic to move a portion of the second region from the multiple level cell mode to the SLC mode.

2. The apparatus of claim 1, wherein data written to the portion of the second region is to be moved to the first region during an idle time between write operations directed at the non-volatile memory.

3. The apparatus of claim 1, comprising logic to move one or more portions of the second region from the multiple level cell mode to the SLC mode to create the first region.

4. The apparatus of claim 1, wherein burst write operations are to be directed at the first region.

5. The apparatus of claim 1, wherein burst write operations are to be directed at the second region in response to a threshold number of burst write operations directed at the first region.

6. The apparatus of claim 1, wherein the multiple level cell mode is a Three Level Cell (TLC) mode.

7. The apparatus of claim 1, wherein the non-volatile memory, the logic, and a Solid State Drive (SSD) are on a same integrated circuit device.

8. The apparatus of claim 1, wherein the non-volatile memory is to comprise one of:

nanowire memory, Ferro-electric transistor random access memory (FeTRAM), magnetoresistive random access memory (MRAM), flash memory, Spin Torque Transfer Random Access Memory (STTRAM), Resistive Random Access Memory, Phase Change Memory (PCM), and byte addressable 3-Dimensional Cross Point Memory.

9. The apparatus of claim 1, wherein an SSD is to comprise the non-volatile memory and the logic.

26. The apparatus of claim 1, wherein the third region is to store data for garbage collection.

10. A method comprising:

partitioning non-volatile memory to include a first region in a Single Level Cell (SLC) mode and a second region in a multiple level cell (MLC) mode, and a third region in the MLC mode, wherein the third region is unexposed as user addressable space; and

moving a portion of the second region from the multiple level cell mode to the SLC mode without adding any new capacity to the non-volatile memory and without reducing any existing capacity from the non-volatile memory.

11. The method of claim 10, further comprising moving data written to the portion of the second region to the first region during an idle time between write operations directed at the non-volatile memory.

12. The method of claim 10, further comprising moving one or more portions of the second region from the multiple level cell mode to the SLC mode to create the first region.

13. The method of claim 10, further comprising directing burst write operations at the first region.

14. The method of claim 10, further comprising directing burst write operations at the second region in response to a threshold number of burst write operations directed at the first region.

15. The method of claim 10, wherein the multiple level cell mode is a Three Level Cell (TLC) mode.

16. The method of claim 10, wherein the non-volatile memory comprises one of:

nanowire memory, Ferro-electric transistor random access memory (FeTRAM), magnetoresistive random access memory (MRAM), flash memory, Spin Torque Transfer Random Access Memory (STTRAM), Resistive Random Access Memory, Phase Change Memory (PCM), and byte addressable 3-Dimensional Cross Point Memory.

17. A system comprising:

non-volatile memory; and

at least one processor core to access the non-volatile memory;

the non-volatile memory to include a first region in a Single Level Cell (SLC) mode and a second region in a multiple level cell (MLC) mode, and a third region in the MLC mode, wherein the third region is to be unexposed as user addressable space; and

logic to move a portion of the second region from the multiple level cell mode to the SLC mode without adding any new capacity to the non-volatile memory and without reducing any existing capacity from the non-volatile memory.

18. The system of claim 17, wherein data written to the portion of the second region is to be moved to the first region during an idle time between write operations directed at the non-volatile memory.

19. The system of claim 17, comprising logic to move one or more portions of the second region from the multiple level cell mode to the SLC mode to create the first region.

20. The system of claim 17, wherein burst write operations are to be directed at the first region.

21. The system of claim 17, wherein burst write operations are to be directed at the second region in response to a threshold number of burst write operations directed at the first region.

22. The system of claim 17, wherein the multiple level cell mode is a Three Level Cell (TLC) mode.

23. The system of claim 17, wherein the non-volatile memory, the logic, and a Solid State Drive (SSD) are on a same integrated circuit device.

24. The system of claim 17, wherein the non-volatile memory is to comprise one of:

nanowire memory, Ferro-electric transistor random access memory (FeTRAM), magnetoresistive random access memory (MRAM), flash memory, Spin Torque Transfer Random Access Memory (STTRAM), Resistive Random Access Memory, Phase Change Memory (PCM), and byte addressable 3-Dimensional Cross Point Memory.

25. The system of claim 17, wherein an SSD is to comprise the non-volatile memory and the logic.