ANALOG NEUROMORPHIC CIRCUIT IMPLEMENTED USING RESISTIVE MEMORIES

• US 20160284400A1
• Filed: 03/28/2016
• Published: 09/29/2016
• Est. Priority Date: 03/27/2015
• Status: Active Grant

• Current Assignee: University of Dayton
• Original Assignee: University of Dayton
• Inventors: Yakopcic, Chris, Hasan, Raqibul, Taha, Tarek M.
• Granted Patent: US 10,474,948 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06N 3/065 Analogue means
• CPC Class Codes: G11C 11/54 using elements simulating biological cells, e.g. neuron
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements

Abstract

An analog neuromorphic circuit is disclosed, having input voltages applied to a plurality of inputs of the analog neuromorphic circuit. The circuit also includes a plurality of resistive memories that provide a resistance to each input voltage applied to each of the inputs so that each input voltage is multiplied in parallel by the corresponding resistance of each corresponding resistive memory to generate a corresponding current for each input voltage and each corresponding current is added in parallel. The circuit also includes at least one output signal that is generated from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel. The multiplying of each input voltage with each corresponding resistance is executed simultaneously with adding each corresponding current for each input voltage.

Claims

1. An analog neuromorphic circuit that implements a plurality of resistive memories, comprising:

a plurality of input voltages applied to a plurality of inputs of the analog neuromorphic circuit;

a plurality of resistive memories configured to provide a resistance to each input voltage applied to each of the inputs so that each input voltage is multiplied in parallel by the corresponding resistance of each corresponding resistive memory to generate a corresponding current for each input voltage and each corresponding current is added in parallel; and

at least one output signal that is generated from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel, wherein multiplying each input voltage with each corresponding resistance is executed simultaneously with adding each corresponding current for each input voltage.

2. The analog neuromorphic circuit of claim 1, further comprising:

a plurality of horizontal wires positioned to intersect with a first pair of vertical wires forming a first wire grid so that each horizontal wire forms a row of the first wire grid and each vertical wire from the first pair of vertical wires forms a column of the first wire grid;

a first plurality of resistive memories with each resistive memory positioned at an intersection of the plurality of horizontal wires and the first pair of vertical wires and configured to;

provide a resistance to each input voltage applied to each horizontal wire so that each input voltage of the first wire grid is multiplied by the corresponding resistance to generate a current relative to each row of the first wire grid that is conducted by a first vertical wire of the first pair of vertical wires and by a second vertical wire of the first pair of vertical wires,

add each current relative to each row of the first wire grid to generate a first accumulative current of the first wire grid that is conducted by the first vertical wire of the first pair of vertical wires and a second accumulative current of the first wire grid that is conducted by the second vertical wire of the first pair of vertical wires; and

a first comparator coupled to the first vertical wire of the first pair of vertical wires at a first input and to the second vertical wire of the first pair of vertical wires at a second input and configured to;

compare a first voltage associated with the first accumulative current of the first wire grid to a second voltage associated with the second accumulative current of the first wire grid, and

generate a first output signal when the first voltage is greater than the second voltage and a second output signal when the second voltage is greater than the first voltage.

3. The analog neuromorphic circuit of claim 2, wherein the first vertical wire is coupled to a bias voltage between a last horizontal wire that has an input voltage and the first input of the first comparator to generate the first voltage associated with the first accumulative current and the second vertical wire is coupled to bias voltage between the last horizontal wire that has the input voltage and the second input of the first comparator to generate the second voltage associated with the second accumulative current.

4. The analog neuromorphic circuit of claim 2, wherein the first comparator is further configured to generate a high voltage signal as the first output signal when the first voltage is greater than the second voltage and a low voltage signal as the second output signal when the second voltage is greater than the first voltage.

5. The analog neuromorphic circuit of claim 2, wherein each resistance provided by each resistive memory is weighted to determine a functionality of the analog neuromorphic circuit.

6. The analog neuromorphic circuit of claim 2, further comprising:

a second pair of vertical wires positioned to intersect relative to the plurality of horizontal wires forming a second wire grid;

a second plurality of resistive memories with each resistive memory positioned at an intersection of the plurality of horizontal wires and the second pair of vertical wires and configured to;

provide a resistance to each input voltage applied to each horizontal wire so that a multiplication of each input voltage of the second wire grid with the corresponding resistance is in parallel with a multiplication of each input voltage with the corresponding resistance of the first wire grid, and

add each current relative to each row of the second wire grid to generate a first accumulative current that is conducted by a first vertical wire of the second pair of vertical wires and a second accumulative current that is conducted by a second vertical wire of the second pair of vertical wires that is in parallel with the adding of the first wire grid; and

a second comparator coupled to the first vertical wire of the second pair of vertical wires at a first input and to the second vertical wire of the second pair at a second input and configured to;

compare a first voltage associated with the first accumulative current of the second wire grid to a second voltage associated with the second accumulative current of the second wire grid, and

generate a first output signal when the first voltage of the second wire grid is greater than the second voltage of the second wire grid and generate a second output signal when the second voltage of the second wire grid is greater than the first voltage of the second wire grid.

7. The analog neuromorphic circuit of claim 6, wherein each input voltage applied to each horizontal wire drives both the first wire grid and the first comparator forming a first neuron and the second wire grid and the second comparator forming a second neuron.

9. The method of claim 1, further comprising:

applying an input voltage to each horizontal wire positioned to intersect a first pair of vertical wires forming a first wire grid so that that each horizontal wire forms a row of the first wire grid and each vertical wire from the first pair of vertical wires forms a column of the first wire grid;

providing a resistance to each input voltage by a first plurality of resistive memories with each resistive memory positioned at an intersection of the plurality of horizontal wires and the first pair of vertical wires of the first wire grid;

multiplying each input voltage by the corresponding resistance to generate a current relative to each row of the first wire grid that is conducted by a first vertical wire of the first pair of vertical wires and by a second vertical wire of the first pair of vertical wires;

adding each current relative to each row of the first wire grid to generate a first accumulative current of the first wire grid that is conducted by the first vertical wire of the first pair of vertical wires and a second accumulative current of the first wire grid that is conducted by the second vertical wire of the first pair of vertical wires;

comparing a first voltage associated with the first accumulative current of the first wire grid to a second voltage associated with the second accumulative current of the first wire grid; and

generating a first output signal when the first voltage is greater than the second voltage and a second output signal when the second voltage is greater than the first voltage.

10. The method of claim 9, further comprising:

generating the first voltage associated with the first accumulative current of the first wire grid by coupling the first vertical wire of the first pair of vertical wires between a last horizontal wire that has an input voltage and a first input of a first comparator coupled to the first vertical wire of the first pair of vertical wires; and

generating the second voltage associated with the second accumulative current of the first wire grid by coupling the second vertical wire of the first pair of vertical wires between the last horizontal wire that has the input voltage and a second input of the first comparator coupled to the second vertical wire of the first pair of vertical wires.

11. The method of claim 9, wherein the generating of the first output signal and the second output signal comprises:

generating a high voltage signal as the first output signal when the first voltage is greater than the second voltage; and

generating a low voltage signal as the second output signal when the second voltage is greater than the first voltage.

12. The method of claim 9, wherein each resistance provided by each resistive memory is weighted to determine a functionality of the analog neuromorphic circuit.

13. The method of claim 9, further comprising:

providing a resistance to each input voltage by a second plurality of resistive memories with each resistive memory positioned at an intersection of the plurality of horizontal wires and a second pair of vertical wires positioned to intersect the plurality of horizontal wires forming a second wire grid;

multiplying each input voltage of the second wire grid with the corresponding resistance in parallel with the multiplying of each input voltage with the corresponding resistance of the first wire grid;

adding each current relative to each row of the second wire grid to generate a first accumulative current that is conducted by the first vertical wire of the second pair of vertical wires and a second accumulative current that is conducted by a second vertical wire of the second pair of vertical wires that is in parallel with the adding of the first wire grid;

comparing a first voltage associated with the first accumulative current of the second wire grid to a second voltage associated with the second accumulative current of the second wire grid; and

generating a first output signal when the first voltage of the second wire grid is greater than the second voltage of the second wire grid and a second output signal when the second voltage of the second wire grid is greater than the first voltage of the second wire grid.

14. The method of claim 13, wherein the applying of the input voltage comprises:

applying each input voltage to each horizontal wire to drive both the first wire grid forming a first neuron and the second wire grid forming a second neuron.

8. A method for generating computation operations in parallel by implementing a plurality of resistive memories, comprising:

applying a plurality of input voltages to a plurality of inputs of an analog neuromorphic circuit;

providing, by a plurality of resistive memories, a resistance to each input voltage applied to each of the inputs so that each input voltage is multiplied in parallel by the corresponding resistance of each corresponding resistive memory to generate a corresponding current for each input voltage and each corresponding current is added in parallel; and

generating at least one output signal from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel, wherein multiplying each input voltage with each corresponding resistance is executed simultaneously with adding each corresponding current for each input voltage.

15. An analog neuromorphic system that implements a plurality of resistive memories, comprising:

a first plurality of wires positioned to intersect with a second plurality of wires forming a first wire grid;

a first plurality of resistive memories with each resistive memory positioned at an intersection of the first plurality of wires and the second plurality of wires and configured to provide a resistance to each input voltage applied to each of the first plurality of wires so that each input voltage of the first wire grid is multiplied in parallel by the corresponding resistance to generate a corresponding current for each input voltage and each corresponding current is added in parallel; and

at least one output signal that is generated from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel, wherein multiplying each input voltage with each corresponding resistance is executed simultaneously with adding each corresponding current for each input voltage.

16. The analog neuromorphic system of claim 15, further comprising:

a first plurality of comparators with each comparator coupled to a pair of wires from the second plurality of wires at a first input and a second input of each comparator and configured to;

compare a magnitude of each voltage that is associated with each respective current conducted by each respective pair of wires from the second plurality of vertical wires that are coupled to each respective first input and second input of each respective comparator, and

generate an output signal that is representative of how the magnitude of each voltage associated with each respective current is compared to each other voltage associated with each respective current that is conducted by each respective pair of wires from the second plurality of vertical wires that are coupled to each respective first input and second input of each respective comparator.

17. The analog neuromorphic system of claim 16, further comprising:

a third plurality of wires positioned to intersect with a fourth plurality of wires forming a second wire grid, wherein each wire from the third plurality of wires is coupled to a respective output of each comparator from the first plurality of comparators;

a second plurality of resistive memories with each resistive memory positioned at an intersection of the third plurality of wires and the fourth plurality of wires and configured to;

provide a resistance to each input voltage applied to each wire of the third plurality of wires so that each input voltage of the second wire grid is multiplied by the corresponding resistance in addition to the multiplication of each input voltage with the corresponding resistance of the first wire grid,

add each current of the second wire grid to generate a plurality of accumulative currents with each accumulative current being conducted by each corresponding wire of the fourth plurality of wires in addition to the adding of the first wire grid; and

a second plurality of comparators with each comparator coupled to a pair of wires from the fourth plurality of wires at a first input and a second input of each comparator from the second plurality of comparators and configured to;

compare a magnitude of each voltage associated with each respective accumulative current conducted by each respective pair of wires from the fourth plurality of wires that are coupled to each respective first input and second input of each respective comparator from the second plurality of comparators, and

generate an output signal that is representative of how the magnitude of each voltage associated with each respective accumulated current is compared to each other voltage associated with each respective accumulated current that is conducted by each respective pair of wires from the fourth plurality of wires that are coupled to each respective input and second input of each respective comparator from the second plurality of comparators.

18. The analog neuromorphic system of claim 17, wherein each input voltage applied to each wire of the first plurality of wires drives both the first wire grid and the first plurality of comparators forming a first layer of neurons of a neural network and the output of each comparator from the first plurality of comparators drives both the second wire grid and the second plurality of comparators forming a second layer of neurons of the neural network.

19. The analog neuromorphic system of claim 18, wherein each resistance provided by each resistive memory associated with the first layer of neurons is weighted to determine a functionality of the first layer of neurons and each resistance provided by each resistive memory associated with the second layer of neurons is weighted to determine a functionality of the second layer of neurons.

20. The analog neuromorphic system of claim 19, wherein each resistance provided by a pair of resistive memories generates a single weight for the pair of restive memories, wherein each pair of resistive memories includes two resistive memories that are positioned on a same wire from the first plurality of wires and/or the third plurality of wires and a same pair of wires from the second plurality of wires and/or the fourth plurality of wires that are coupled to a first output and a second output of a same comparator.