ANALOG NEUROMORPHIC CIRCUIT IMPLEMENTED USING RESISTIVE MEMORIES
First Claim
1. An analog neuromorphic circuit that implements a plurality of resistive memories, comprising:
- a plurality of input voltages applied to a plurality of inputs of the analog neuromorphic circuit;
a plurality of resistive memories configured to provide a resistance to each input voltage applied to each of the inputs so that each input voltage is multiplied in parallel by the corresponding resistance of each corresponding resistive memory to generate a corresponding current for each input voltage and each corresponding current is added in parallel; and
at least one output signal that is generated from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel, wherein multiplying each input voltage with each corresponding resistance is executed simultaneously with adding each corresponding current for each input voltage.
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Abstract
An analog neuromorphic circuit is disclosed, having input voltages applied to a plurality of inputs of the analog neuromorphic circuit. The circuit also includes a plurality of resistive memories that provide a resistance to each input voltage applied to each of the inputs so that each input voltage is multiplied in parallel by the corresponding resistance of each corresponding resistive memory to generate a corresponding current for each input voltage and each corresponding current is added in parallel. The circuit also includes at least one output signal that is generated from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel. The multiplying of each input voltage with each corresponding resistance is executed simultaneously with adding each corresponding current for each input voltage.
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Citations
20 Claims
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1. An analog neuromorphic circuit that implements a plurality of resistive memories, comprising:
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a plurality of input voltages applied to a plurality of inputs of the analog neuromorphic circuit; a plurality of resistive memories configured to provide a resistance to each input voltage applied to each of the inputs so that each input voltage is multiplied in parallel by the corresponding resistance of each corresponding resistive memory to generate a corresponding current for each input voltage and each corresponding current is added in parallel; and at least one output signal that is generated from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel, wherein multiplying each input voltage with each corresponding resistance is executed simultaneously with adding each corresponding current for each input voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14)
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8. A method for generating computation operations in parallel by implementing a plurality of resistive memories, comprising:
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applying a plurality of input voltages to a plurality of inputs of an analog neuromorphic circuit; providing, by a plurality of resistive memories, a resistance to each input voltage applied to each of the inputs so that each input voltage is multiplied in parallel by the corresponding resistance of each corresponding resistive memory to generate a corresponding current for each input voltage and each corresponding current is added in parallel; and generating at least one output signal from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel, wherein multiplying each input voltage with each corresponding resistance is executed simultaneously with adding each corresponding current for each input voltage.
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15. An analog neuromorphic system that implements a plurality of resistive memories, comprising:
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a first plurality of wires positioned to intersect with a second plurality of wires forming a first wire grid; a first plurality of resistive memories with each resistive memory positioned at an intersection of the first plurality of wires and the second plurality of wires and configured to provide a resistance to each input voltage applied to each of the first plurality of wires so that each input voltage of the first wire grid is multiplied in parallel by the corresponding resistance to generate a corresponding current for each input voltage and each corresponding current is added in parallel; and at least one output signal that is generated from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel, wherein multiplying each input voltage with each corresponding resistance is executed simultaneously with adding each corresponding current for each input voltage. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification