PACKAGE SUBSTRATE AND PACKAGE STRUCTURE USING THE SAME

• US 20160284666A1
• Filed: 03/18/2016
• Published: 09/29/2016
• Est. Priority Date: 03/18/2015
• Status: Active Grant

• Current Assignee: Nichia Corporation
• Original Assignee: Genesis Photonics Inc.
• Inventors: Lee, Hao-Chung, Lin, Yu-Feng, Zhan, Xun-Xain
• Granted Patent: US 9,953,956 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/49107 on the semiconductor or solid-state body
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/0753 the devices being arranged next to each other
• CPC Class Codes: H01L 25/0756 Stacked arrangements of devices
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/15 including semiconductor components having potential barriers, specially adapted for light emission
• CPC Class Codes: H01L 29/866 Zener diodes
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/18161 of a flip chip
• CPC Class Codes: H01L 2933/0025 relating to coatings
• CPC Class Codes: H01L 2933/0033 relating to semiconductor body packages
• CPC Class Codes: H01L 2933/0041 relating to wavelength conversion elements
• CPC Class Codes: H01L 2933/0058 relating to optical field-shaping elements
• CPC Class Codes: H01L 33/08 with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body H01L27/15 takes precedence
• CPC Class Codes: H01L 33/10 with a light reflecting structure, e.g. semiconductor Bragg reflector
• CPC Class Codes: H01L 33/48 : characterised by the semiconductor body packages
• CPC Class Codes: H01L 33/486 : adapted for surface mounting
• CPC Class Codes: H01L 33/50 : Wavelength conversion elements
• CPC Class Codes: H01L 33/502 : Wavelength conversion materials
• CPC Class Codes: H01L 33/508 : having a non-uniform spatial arrangement or non-uniform concentration, e.g. patterned wavelength conversion layer, wavelength conversion layer with a concentration gradient of the wavelength conversion material
• CPC Class Codes: H01L 33/52 : Encapsulations
• CPC Class Codes: H01L 33/56 : Materials, e.g. epoxy or silicone resin
• CPC Class Codes: H01L 33/60 : Reflective elements
• CPC Class Codes: H01L 33/642 : characterized by the shape
• CPC Class Codes: H01L 33/647 : the elements conducting electric current to or from the semiconductor body

Abstract

A package substrate is provided. The package substrate includes a base layer having a first surface and a second surface opposite to the first surface, a plurality of through holes penetrating the base layer, a first metal layer disposed on the first surface, and a second metal layer disposed on the second surface. The first metal layer includes a closed-loop trench. A part of the second metal layer is electrically connected to the first metal layer via the through holes. The through holes are positioned at an inner part the closed-loop trench.

Claims

1. A package substrate, comprising:

a base layer having a first surface and a second surface opposite to the first surface;

a plurality of through holes penetrating the base layer;

a first metal layer disposed on the first surface and comprising a closed-loop trench; and

a second metal layer disposed on the second surface, wherein a part of the second metal layer is electrically connected to the first metal layer via the through holes;

wherein the through holes are positioned at an inner part of the closed-loop trench.

2. The package substrate according to claim 1, further comprising:

a separation structure disposed on the first surface;

wherein the separation structure is connected with the closed-loop trench.

3. The package substrate according to claim 1, wherein the second metal layer further comprises:

a heat dissipation region formed of a plurality of trenches arranged in a polygonal or curved array.

4. The package substrate according to claim 1, wherein a width of the closed-loop trench is from 80 to 300 μ

m.

5. The package substrate according to claim 1, wherein a depth of the closed-loop trench is from 40 to 80 μ

m.

6. The package substrate according to claim 1, wherein the base layer is formed of a ceramic material.

7. A package structure, comprising:

a package substrate, comprising;

a base layer having a first surface and a second surface opposite to the first surface;

a plurality of through holes penetrating the base layer;

a first metal layer disposed on the first surface and comprising a closed-loop trench; and

a second metal layer disposed on the second surface, wherein a part of the second metal layer is electrically connected to the first metal layer via the through holes; and

a chipset and an encapsulant layer disposed on the first metal layer and positioned at an inner part of the closed-loop trench.

8. The package structure according to claim 7, wherein the package substrate further comprises:

a separation structure disposed on the first surface;

wherein the chipset is disposed on the separation structure and the separation structure is connected with the closed-loop trench.

9. The package structure according to claim 7, wherein the second metal layer further comprising:

a heat dissipation region corresponding to the chipset;

wherein the heat dissipation region is formed of a plurality of trenches arranged in a polygonal or curved array.

10. The package structure according to claim 9, wherein the second metal layer further comprises:

an anode region and a cathode region separated from the heat dissipation region;

wherein each of a distance between the anode region and the cathode region, a distance between the anode region and the heat dissipation region, and a distance between the cathode region and the heat dissipation region is at least 400 μ

m.

11. The package structure according to claim 7, wherein the chipset comprises only one single rectangular chip.

12. The package structure according to claim 7, wherein the chipset comprises a plurality of chips.

13. The package structure according to claim 12, wherein distances between the chips are 50 μ

m.

14. The package structure according to claim 7, wherein a distance between the closed-loop trench and the chipset is from 500 to 2000 μ

m.

15. The package structure according to claim 7, wherein the encapsulant layer covers the chipset.

16. The package structure according to claim 15, wherein the encapsulant layer comprises phosphor powder.

17. The package structure according to claim 7, further comprising:

a wavelength conversion layer disposed on a top surface of the chipset;

wherein the encapsulant layer is disposed on a lateral surface of the chipset.

18. The package structure according to claim 7, wherein the package substrate further comprises:

a plating layer formed on the first metal layer and the second metal layer;

wherein the plating layer is formed of gold or silver.

19. A manufacturing method of package structure, comprising:

providing a package substrate comprising a base layer, a first metal layer and a second metal layer, wherein the base layer has a first surface and a second surface opposite to the first surface, the first metal layer is disposed on the first surface and comprises a closed-loop trench, and the second metal layer is disposed on the second surface;

providing a chipset on the first metal layer; and

providing an encapsulant layer on the first metal layer;

wherein the chipset and the encapsulant layer are disposed on an inner side of the closed-loop trench.

20. The manufacturing method of package structure according to claim 19, further comprising:

forming a wavelength conversion layer on a top surface of the chipset;

wherein the encapsulant layer is disposed on a lateral surface of the chipset and the wavelength conversion layer.