NAND MEMORY STRINGS AND METHODS OF FABRICATION THEREOF

• US 20160284730A1
• Filed: 06/10/2016
• Published: 09/29/2016
• Est. Priority Date: 10/24/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: KANAKAMEDALA, Senaka, KOKA, Sateesh, MAKALA, Raghuveer S., ZHANG, Yanli, SHARANGPANI, Rahul, LEE, Yao-Sheng, MATAMIS, George
• Granted Patent: US 9,646,990 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7889 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

Methods of making monolithic three-dimensional memory devices include performing a first etch to form a memory opening and a second etch using a different etching process to remove a damaged portion of the semiconductor substrate from the bottom of the memory opening. A single crystal semiconductor material is formed over the substrate in the memory opening using an epitaxial growth process. Additional embodiments include improving the quality of the interface between the semiconductor channel material and the underlying semiconductor layers in the memory opening which may be damaged by the bottom opening etch, including forming single crystal semiconductor channel material by epitaxial growth from the bottom surface of the memory opening and/or oxidizing surfaces exposed to the bottom opening etch and removing the oxidized surfaces prior to forming the channel material. Monolithic three-dimensional memory devices formed by the embodiment methods are also disclosed.

Claims

1. A method of fabricating a memory device, comprising:

forming a material layer stack over a major surface of a semiconductor substrate;

etching the stack through a mask to the semiconductor substrate using a first etching process to form a memory opening having a sidewall defined at least in part by the stack and a bottom surface that is defined by the semiconductor substrate;

etching through the memory opening using a second etching process that is different from the first etching process to remove a damaged portion of the semiconductor substrate from the bottom surface of the memory opening;

forming a single crystal semiconductor material over the semiconductor substrate on the bottom surface of the memory opening using an epitaxial growth process;

forming at least one memory film on at least a portion of the sidewall of the memory opening and over the single crystal semiconductor material on the bottom surface of the memory opening;

forming a layer of semiconductor material over the at least one memory film on at least a portion of the sidewall of the memory opening and on the bottom surface of the memory opening;

etching through the memory opening using a third etching process to remove a portion of the layer of semiconductor material and a portion of the at least one memory film from over the bottom surface of the memory opening and expose the single crystal semiconductor material on the bottom surface of the memory opening; and

forming a semiconductor channel material over the layer of semiconductor material on the sidewall of the memory opening and over the single crystal semiconductor material on the bottom surface of the memory opening.

2. The method of claim 1, wherein:

forming the layer of semiconductor material comprises forming a layer of polycrystalline or amorphous semiconductor material;

forming the semiconductor channel material comprises forming a single crystal semiconductor layer of channel material over the layer of polycrystalline or amorphous semiconductor material; and

the single crystal semiconductor layer of channel material is formed by epitaxial growth from the single crystal semiconductor material exposed on the bottom surface of the memory opening.

3. The method of claim 2, wherein the semiconductor substrate comprises a silicon substrate, the single crystal semiconductor material formed over the semiconductor substrate on the bottom surface of the memory opening comprises single crystal silicon, the layer of polycrystalline or amorphous semiconductor material comprises polysilicon, and the single crystal semiconductor layer of channel material comprises single crystal silicon.

4. The method of claim 3, wherein the third etching process is different from the first etching process.

5. The method of claim 4, wherein the single crystal semiconductor layer of channel material is formed over portions of the layer of polycrystalline or amorphous semiconductor material and the single crystal semiconductor material exposed on the bottom surface of the memory opening that are damaged by the third etching process to at least partially heal the damage.

6. The method of claim 2, wherein forming the material layer stack over the major surface of the substrate comprises forming an initial oxide layer on the major surface of the substrate having a height above the major surface of the substrate, and wherein forming the single crystal semiconductor material over the semiconductor substrate on the bottom surface of the memory opening comprises forming the single crystal semiconductor material to at least the planar level of the initial oxide layer.

7. The method of claim 2, wherein etching through the memory opening to remove a portion of the layer of polycrystalline or amorphous semiconductor material and a portion of the at least one memory film from over the bottom surface of the memory opening comprises forming a generally cylindrically-shaped opening through the layer of polycrystalline or amorphous semiconductor material and the at least one memory film, wherein the generally cylindrically-shaped opening comprises a sidewall defined by the layer of polycrystalline or amorphous semiconductor material and the at least one memory film and a bottom surface that is defined by the single crystal semiconductor material exposed on the bottom surface of the memory opening.

8. The method of claim 7, wherein forming the single crystal semiconductor layer of channel material comprises:

forming a first portion of the layer of channel material by epitaxial growth from the single crystal semiconductor material exposed on the bottom surface of the generally cylindrically-shaped opening in a first direction that is substantially perpendicular to the major surface of the substrate;

forming a second portion of the layer of channel material by epitaxial growth from the generally cylindrically shaped opening in a second direction that is substantially parallel to the major surface of the substrate over the bottom surface of the memory opening; and

forming a third portion of the layer of channel material by epitaxial growth from the bottom surface of the memory opening in the first direction that is substantially perpendicular to the major surface of the substrate over the sidewall of the memory opening.

9. The method of claim 1, further comprising:

forming an oxide layer on the sidewall and bottom surface of the memory opening by surface oxidation of the layer of semiconductor material and the single crystal semiconductor material exposed on the bottom surface of the memory opening; and

removing the oxide layer from the sidewall and bottom surface of the memory opening.

10. The method of claim 9, wherein the semiconductor substrate comprises a silicon substrate, the single crystal semiconductor material formed over the semiconductor substrate on the bottom surface of the memory opening comprises single crystal silicon, the layer of semiconductor material comprises polysilicon, and the semiconductor channel material comprises at least one of polysilicon and epitaxial single crystal silicon.

11. The method of claim 10, wherein the oxide layer is formed on the sidewall and bottom surface of the memory opening by oxidizing surfaces of the layer of semiconductor material and the single crystal semiconductor material that are damaged by the third etching process.

12. The method of claim 11, wherein the oxide layer is removed by a fourth etching process that is different than the first etching process and selectively etches the oxide material without removing the layer of semiconductor material and the single crystal semiconductor material on the bottom surface of the memory opening.

13. The method of claim 12, wherein:

the at least one memory film comprises a cover oxide layer, a layer of charge storage material over the cover oxide layer, and a tunnel oxide layer over the layer of charge storage material; and

the fourth etching process removes at least a portion of the cover oxide layer and the tunnel oxide layer from over the bottom surface of the memory opening to provide a first recess extending substantially parallel to the bottom surface of the memory opening between the exposed surface of the single crystal semiconductor material and the layer of charge storage material and a second recess extending substantially parallel to the bottom surface of the memory opening between the layer of charge storage material and the layer of semiconductor material.

14. The method of claim 13, wherein the layer of charge storage material comprises silicon nitride and wherein the fourth etching process comprises a wet chemical etch using hydrofluoric acid.

15. The method of claim 13, wherein forming the semiconductor channel material comprises filling the first and the second recessed portions.

16. The method of claim 1, wherein the first etching process comprises a reactive ion etching (RIE) process, and the second etching process removes the damaged portion of the semiconductor substrate that is damaged by the RIE etching.

17. The method of claim 16, wherein the second etching process comprises at least one of a dilute HF wet etch, a chlorine based dry etch, a hydrochloric acid (HCL) based dry etch and a bromine (Br) based dry etch.

18. The method of claim 1, wherein the semiconductor channel material extending substantially perpendicular to the major surface of the substrate forms an end portion of a semiconductor channel of a NAND string, wherein the stack comprises:

a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate, wherein the plurality of control gate electrodes comprises at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level; and

an first insulating material layer located between the first control gate electrode and the second control gate electrode, and the at least one memory film over the sidewall of the memory opening is located between each of the plurality of control gate electrodes and the semiconductor channel.

19. The method of claim 18, wherein forming the stack comprises:

forming an alternating plurality of first insulating material layers and second sacrificial material layers, the method further comprising;

forming a back side opening through the stack;

etching through the back side opening to remove at least a portion of the second sacrificial layers and form back side recesses between the first insulating material layers; and

forming a blocking dielectric and a plurality of control gate electrodes through the back side opening within the back side recesses.