DRIVE FOR CASCODE STACK OF POWER FETS

• US 20160285454A1
• Filed: 03/27/2015
• Published: 09/29/2016
• Est. Priority Date: 03/27/2015
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Yung, Chifan, Gupta, Vishal, Duncan, Joseph
• Granted Patent: US 9,548,739 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03F 2203/30015 An input signal dependent control signal controls the bias of an output stage in the SEPP
• CPC Class Codes: H03F 2203/30084 the pull circuit of the SEPP amplifier being a cascode circuit
• CPC Class Codes: H03F 2203/30099 the pull transistor being gated by a switching element
• CPC Class Codes: H03F 2203/30117 the push circuit of the SEPP amplifier being a cascode circuit
• CPC Class Codes: H03F 2203/30132 the push transistor being gated by a switching element
• CPC Class Codes: H03F 3/2173 of the bridge type
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 19/018507 Interface arrangements

Abstract

Disclosed is a cascode configuration that moves the gate of the cascode substantially without delay relative to an output node by capacitively coupling the latter onto the cascode gates. The passive coupling eliminates the need for actively driving the gates of the cascode. In some embodiments, the only circuitry needed on the cascode gate may be a biasing circuit that limits the swing on the cascode gate between V_max and 2×V_max, where V_max is a transistor device rating.

Claims

1. A circuit comprising:

a transistor stack comprising a series connection of a first transistor device, a second transistor device, and an output transistor device, the output transistor device having an output terminal and a control terminal, the first transistor device having an input terminal configured for a connection to a control voltage;

a capacitive coupling between the control terminal and the output terminal configured to drive the control terminal with a coupled signal that continuously tracks an output signal on the output terminal; and

a biasing circuit connected to the control terminal of the output transistor device, the biasing circuit configured to provide a DC bias voltage that is combined with the coupled signal to provide a drive signal on the control terminal, the biasing circuit further configured to respond to changes in a voltage level of the drive signal substantially with no delay in order to maintain a voltage level of the DC bias voltage between a first voltage level and a second voltage level.

2. The circuit of claim 1, wherein the second transistor device is a cascode of the first transistor device, wherein the capacitive coupling comprises a first capacitance between the control terminal of the output transistor device and the output terminal of the output transistor device,

the circuit further comprising a second capacitance between the input terminal of the first transistor device and the control terminal of the output transistor device.

3. The circuit of claim 1, wherein the capacitive coupling between the control terminal of the output transistor device and the output terminal of the output transistor device comprises a parasitic capacitance between the control terminal and the output terminal.

4. The circuit of claim 1, wherein the capacitive coupling between the control terminal of the output transistor device and the output terminal of the output transistor device comprises a capacitor connected between the control terminal and the output terminal.

5. The circuit of claim 1, further comprising:

a fourth transistor device;

a fifth transistor device connected as a cascode of the fourth transistor device;

a second output transistor device connected as a cascode of the fifth transistor device, the second output transistor device having an output terminal and a control terminal;

a capacitive coupling between the control terminal and the output terminal configured to drive the control terminal with a coupled signal that continuously tracks an output signal on the output terminal; and

a biasing circuit connected to the control terminal, the biasing circuit configured to provide a DC bias voltage that is combined with the coupled signal to provide a drive signal on the control terminal, the biasing circuit further configured to respond without delay to changes in a voltage level of the drive signal in order to maintain a voltage level of the DC bias voltage between a first voltage level and a second voltage level.

6. The circuit of claim 5, wherein the capacitive coupling between the control terminal of the second output transistor device and the output terminal of the second output transistor device comprises a parasitic capacitance between the control terminal and the output terminal.

7. The circuit of claim 5, wherein the capacitive coupling between the control terminal of the second output transistor device and the output terminal of the second output transistor device comprises a capacitor connected between the control terminal and the output terminal.

8. A circuit comprising:

a first stack comprising a first transistor, a second transistor, and a third transistor, the third transistor comprising a control terminal and an output terminal;

a second stack connected to the first stack at a node;

a biasing circuit connected to the control terminal of the third transistor; and

a capacitive coupling between the control terminal of the third transistor and the output terminal of the third transistor configured to couple an output signal at the output terminal as a coupled signal to the control terminal,

the biasing circuit configured to provide a DC bias voltage that combines with the coupled signal to produce a drive signal on the control terminal, the biasing circuit further configured to respond to changes in a voltage level of the drive signal with substantially no delay and maintain a voltage level of the DC bias voltage between a first voltage level and a second voltage level as the voltage level of the drive signal changes.

9. The circuit of claim 8, wherein the capacitive coupling comprises a parasitic capacitance between the output terminal of the third transistor device and the control terminal of the third transistor device.

10. The circuit of claim 8, wherein the capacitive coupling comprises an explicit capacitor between the output terminal of the third transistor device and the control terminal of the third transistor device.

11. The circuit of claim 8, further comprising a capacitor connected between the first transistor device and the third transistor device.

12. The circuit of claim 8, wherein the second stack comprises:

a fourth transistor device;

a fifth transistor device connected as a cascode of the fourth transistor device;

a sixth transistor device connected as a cascode of the fifth transistor device, the sixth transistor device having an output terminal and a control terminal;

a capacitive coupling between the control terminal of the sixth transistor device and the output terminal of the sixth transistor device configured to couple to the control terminal with a coupled signal that continuously tracks an output signal on the output terminal of the sixth transistor device; and

a biasing circuit configured to provide a DC bias voltage that combines with the coupled signal to produce a drive signal on the control terminal, the biasing circuit further configured to respond to changes in a voltage level of the drive signal substantially with no delay to maintain a voltage level of the DC bias voltage between a first voltage level and a second voltage level as the voltage level of the drive signal changes.

13. A method in a transistor comprising:

providing a divided output signal at an output terminal of the transistor as a coupled signal to a control terminal of the transistor using a capacitive coupling between the output terminal and the control terminal;

generating a DC bias voltage;

providing a drive signal on the control terminal of the transistor by combining the DC bias voltage with the coupled signal; and

responding, substantially without delay, to variations in a voltage level of the drive signal by maintaining a voltage level of the DC bias voltage between a first voltage level and a second voltage level,

wherein the capacitive coupling comprises a first capacitor connected between the output terminal and the control terminal and a second capacitor connected between a power rail and the control terminal to define a capacitive voltage divider.

14. The method of claim 13, wherein the first capacitor comprises a parasitic capacitance between the output terminal and the control terminal.

15. The method of claim 14, wherein the first capacitor comprises a physical capacitor.

16. (canceled)

17. A circuit comprising:

means for providing a divided output signal at an output terminal of a transistor in the circuit as a coupled signal to a control terminal of the transistor using a capacitive coupling between the output terminal and the control terminal;

means for generating a DC bias voltage;

means for providing a drive signal on the control terminal of the transistor by combining the DC bias voltage with the coupled signal; and

means for responding, substantially without delay, to variations in a voltage level of the drive signal to maintain a voltage level of the DC bias voltage between a first voltage level and a second voltage level,

wherein the capacitive coupling comprises a first capacitor connected between the output terminal and the control terminal and a second capacitor connected between a power rail and the control terminal to define a capacitive voltage divider.

18. The circuit of claim 17, wherein the first capacitor comprises a parasitic capacitance between the output terminal and the control terminal.

19. The circuit of claim 18, wherein the first capacitor comprises a physical capacitor.

20. (canceled)