ARRAY SUBSTRATE AND DRIVE METHOD THEREOF, TOUCH CONTROL DISPLAY PANEL, AND DISPLAY APPARATUS

• US 20160291751A1
• Filed: 08/21/2015
• Published: 10/06/2016
• Est. Priority Date: 04/01/2015
• Status: Active Grant

• Current Assignee: Shanghai Tianma Micro-Electronics Company Limited (Tianma Microelectronics Company Limited), Tianma Microelectronics Company Limited
• Original Assignee: Shanghai Tianma Micro-Electronics Company Limited (Tianma Microelectronics Company Limited), Tianma Microelectronics Company Limited
• Inventors: MA, Conghua, YAO, Qijun, YANG, Kang
• Granted Patent: US 9,857,899 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/04164 Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
• CPC Class Codes: G06F 3/04184 Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally
• CPC Class Codes: G06F 3/0443 using a single layer of sensing electrodes
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52

Abstract

An array substrate and a drive method thereof, a touch control display and a display apparatus are provided. An array substrate includes, in part, a gate line layer configured with a multitude of gate lines, and a common electrode layer configured with a multitude of common electrodes. The common electrodes further operate as touch control electrodes with a projection on the array substrate along a direction substantially perpendicular to the array substrate. The projection covers n gate lines, where n is a positive integral number. At least one of the touch control electrodes comprises n sub common electrodes each having a projection on the array substrate along the direction substantially perpendicular to the array substrate covering one of the gate lines. Accordingly, less flicks or stripes appear on the display.

Claims

1. An array substrate, comprising:

a gate line layer configured with a plurality of gate lines; and

a common electrode layer configured with a plurality of common electrodes;

wherein the plurality of common electrodes also serve as touch control electrodes, the touch control electrodes having a projection on the array substrate along a direction perpendicular to the array substrate and the projection covering n gate lines; and

wherein at least one of the touch control electrodes comprises n sub common electrodes, each sub common electrode having a projection on the array substrate along the direction perpendicular to the array substrate covering one of the plurality of gate lines, where n is a positive integral number.

2. The array substrate of claim 1, further comprising a plurality of signal input terminals, wherein each sub common electrode is connected with one of the plurality of signal input terminals.

3. The array substrate of claim 1, wherein the sub common electrodes are grouped into at least k sub common electrode sets which are respectively defined as a 1^st sub common electrode set to a k^th sub common electrode set;

wherein k is an integral number not less than 2 and not greater than n, and wherein a value of k matches with gate drive signals input into the plurality of gate lines;

wherein the n gate lines covered by the projection of the touch control electrode are respectively defined as a 1^st gate line to a n^th gate line based on a sequence according to which the n gate lines are driven;

wherein regarding a i^th sub common electrode set, if all the one or more sub common electrodes contained therein correspond to a r^th gate line, then the value of r is calculated based on Equation (i);

r=i+a*k  

 

Equation (i)

where

4. The array substrate of claim 3, wherein a high level of the gate drive signal input into a t^th gate line and a high level of the gate drive signal input into a w^th gate line are not overlapped, and a high level of the gate drive signal input into a (t−

1)^th gate line and the high level of the gate drive signal input into the w^th gate line are overlapped, where k=t−

w, w<

t≦

n, and both t and w are positive integral numbers.

5. The array substrate of claim 3, wherein within each sub common electrode set, all the sub common electrodes are electrically connected.

6. The array substrate of claim 4, wherein within each sub common electrode set, all the sub common electrodes are electrically connected.

7. The array substrate of claim 5, further comprising k signal input terminals, wherein each sub common electrode set is electrically connected with one of the k signal input terminals.

8. The array substrate of claim 6, further comprising k signal input terminals, wherein each sub common electrode set is electrically connected with one of the k signal input terminals.

9. The array substrate of claim 5, further comprising a signal input terminal, wherein all the sub common electrode sets are electrically connected with each other and all the sub common electrode sets are electrically connected with a common signal input terminal.

10. The array substrate of claim 6, further comprising a signal input terminal, wherein all the sub common electrode sets are electrically connected with each other and all the sub common electrode sets are electrically connected with a common signal input terminal.

11. The array substrate of claim 3, further comprising signal lines, wherein all the sub common electrodes in a same sub common electrode set are electrically connected through the signal lines.

12. The array substrate of claim 4, further comprising signal lines, wherein all the sub common electrodes in a same sub common electrode set are electrically connected through the signal lines.

13. The array substrate of claim 11, further comprising metal via holes, wherein the signal lines are metal lines which are electrically connected with all the sub common electrodes in the sub common electrode sets through the metal via holes.

14. The array substrate of claim 12, further comprising metal via holes, wherein the signal lines are metal lines which are electrically connected with all the sub common electrodes in the sub common electrode sets through the metal via holes.

15. The array substrate of claim 1, wherein the touch control electrodes are arranged in an array, and dimensions of the touch control electrodes that are located in a common column decrease progressively.

16. The array substrate of claim 1, wherein the sub common electrodes, which cover at most (k−

1) neighboring gate lines, are electrically connected with each other, where 3≦

k≦

n, and k is an integral number; and

a high level of the gate drive signal input into a t^th gate line and a high level of the gate drive signal input into a w^th gate line are not overlapped, and a high level of the gate drive signal input into a (t−

1)^th gate line and the high level of the gate drive signal input into the w^th gate line are overlapped, where k=t−

w, w<

t≦

n, and both t and w are positive integral numbers.

17. The array substrate of claim 3, configured to include a drive method, the method comprising:

implementing a driving process to the plurality of gate lines on the array substrate by pulse signals;

wherein high levels of the pulse signals input into the neighboring k gate lines are overlapped.

18. A touch control display, comprising an array substrate, wherein the array substrate comprises:

a gate line layer configured with a plurality of gate lines; and

a common electrode layer configured with a plurality of common electrodes;

wherein the plurality of common electrodes also serve as touch control electrodes, the touch control electrodes having a projection on the array substrate along a direction perpendicular to the array substrate and the projection covering n gate lines; and

wherein at least one of the touch control electrodes comprises n sub common electrodes, each sub common electrode having a projection on the array substrate along the direction perpendicular to the array substrate covering one of the gate lines, where n is a positive integral number.