SYSTEMS, METHODS, AND APPARATUS FOR CONTROLLING THE POWER-ON OR BOOT SEQUENCE OF AN INTEGRATED CIRCUIT BASED ON POWER HARVESTING CONDITIONS

• US 20160291983A1
• Filed: 12/08/2015
• Published: 10/06/2016
• Est. Priority Date: 04/06/2015
• Status: Active Grant

• Current Assignee: Everactive, Inc.
• Original Assignee: PsiKick, Inc
• Inventors: Calhoun, Benton H., Wentzloff, David D.
• Granted Patent: US 9,558,008 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0632 by initialisation or re-initialisation of storage systems
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57
• CPC Class Codes: G06F 9/445 Program loading or initiating bootstrapping G06F9/4401; security arrangements for program loading or initiating G06F21/57
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In some embodiments, an apparatus includes an integrated circuit such as a system on chip that operates in part from harvested power and that uses information about power harvesting conditions to alter a power-on sequence or boot sequence based on that information. In some embodiments, a method uses information about power harvesting and energy harvesting conditions to alter a power-on sequence or boot sequence.

Claims

1-7. -7. (canceled)

8. An apparatus, comprising:

an energy harvesting circuit;

an integrated circuit (IC) operatively coupled to the energy harvesting circuit;

a memory operatively coupled to the IC; and

a boot override component configured to receive information associated with a harvested energy harvested by the energy harvesting circuit,

the boot override component configured to, in response to a boot request for the IC and based on the information, modify an operation associated with the memory to define a modified boot sequence such that the IC executes the modified boot sequence in response to the boot request.

9. The apparatus of claim 8, wherein the boot override component is configured to modify the operation associated with the memory by modifying a level of at least one pin of the memory, independent of the operation of the memory.

10. The apparatus of claim 8, further comprising:

a multiplexer operatively coupled to the boot override component and the memory, the multiplexer configured to replace a first output value of the memory with a second output value different from the first output value.

11. The apparatus of claim 8, wherein the boot override component is configured to modify the operation associated with the memory by modifying a jump operand for a conditional jump for the memory within the modified boot sequence.

12. The apparatus of claim 8, wherein the boot override component is configured to modify the operation associated with the memory by modifying a jump location for the memory within the modified boot sequence.

13. The apparatus of claim 8, further comprising:

a power management unit (PMU) operatively coupled to the boot override component,

the energy harvesting circuit, the IC and the PMU being included within a system on chip (SoC),

the boot override component configured to modify an operation of the PMU such that the operation associated with the memory is modified to define the modified boot sequence.

14. The apparatus of claim 8, wherein the boot override component is configured to modify the operation associated with the memory by modifying at least one of an amount of data accessed in the memory, a rate of data accessed in the memory, or a pattern of data accessed in the memory.

21. The apparatus of claim 8, further comprising an energy storage element operatively coupled to the boot override component.

22. The apparatus of claim 8, wherein the boot override component is further configured to receive information associated with a stored energy stored at an energy storage element.

23. The apparatus of claim 8, wherein the boot override component is further configured to receive information associated with a stored energy stored at an energy storage element, and

the boot override component modifies the operation associated with the memory based on the information associated with the harvested energy, the information associated with the stored energy and a minimal boot energy to execute the boot request.

24. The apparatus of claim 8, wherein the memory is a first memory that is a volatile memory, the apparatus further comprising a second memory that is a non-volatile memory.

15-20. -20. (canceled)

25. An apparatus, comprising:

an integrated circuit (IC);

a memory operatively coupled to the IC; and

a boot override component configured to receive information associated with an amount of energy available to the IC,

the boot override component configured to, in response to a boot request for the IC and based on the information, modify an operation associated with the memory to define a modified boot sequence such that the IC executes the modified boot sequence in response to the boot request.

26. The apparatus of claim 25, further comprising an energy storage element operatively coupled to the boot override component.

27. The apparatus of claim 25, wherein the modification of the operation includes bypassing the memory to load a boot code from another source, the modified boot sequence corresponding to the boot code.

28. The apparatus of claim 25, wherein the modification of the operation includes modifying at least one of an amount of data accessed in the memory, a rate of data accessed in the memory, or a pattern of data accessed in the memory.

29. A non-transitory computer readable medium, the medium storing instructions configured to cause a boot override component to:

receive information associated with an operation of an integrated circuit (IC); and

modify, in response to a boot request for the IC and based on the information, an operation associated with a memory that is operatively coupled to the IC, the modification of the operation defining a modified boot sequence such that the IC executes the modified boot sequence in response to the boot request.

30. The medium of claim 29, wherein the information includes an indication of energy available to the IC to execute the boot request.

31. The medium of claim 29, wherein the information includes an indication of energy available to the IC to execute the boot request, the energy including a harvested energy harvested by an energy harvesting circuit operatively coupled to the IC.

32. The medium of claim 29, wherein the information includes an indication of energy available to the IC to execute the boot request, the energy including a stored energy stored by an energy storage element operatively coupled to the IC.

33. The medium of claim 29, wherein the modification of the operation includes modifying at least one of an amount of data accessed in the memory, a rate of data accessed in the memory, or a pattern of data accessed in the memory.