VIRTUAL REGISTER FILE

• US 20160292080A1
• Filed: 03/30/2016
• Published: 10/06/2016
• Est. Priority Date: 04/01/2015
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Rogers, Geoffrey C., Leidel, John D.
• Granted Patent: US 10,049,054 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/109 for multiple virtual address spaces, e.g. segmentation G06F12/1036 takes precedence
• CPC Class Codes: G06F 2212/65 Details of virtual memory and virtual address translation
• CPC Class Codes: G06F 8/441 Register allocation; Assignment of physical memory space to logical memory space

Abstract

The present disclosure is related to a virtual register file. Source code can be compiled to include references to a virtual register file for data subject to a logical operation. The references can be dereferenced at runtime to obtain physical addresses of memory device elements according to the virtual register file. The logical operation can be performed in the memory device on data stored in the memory device elements.

Claims

1. A method, comprising:

compiling source code to include references to a virtual register file for data subject to a logical operation; and

dereferencing the references at runtime to obtain physical addresses of memory device elements according to the virtual register file,

wherein the logical operation is to be performed in a memory device on data stored in the memory device elements.

2. The method of claim 1, wherein compiling the source code comprises compiling the source code at a host coupled to the memory device.

3. The method of claim 1, wherein the references to the virtual register file comprise indices to virtual vector registers in the virtual register file.

4. The method of claim 3, wherein the method includes storing virtual addresses in the virtual vector registers.

5. The method of claim 1, wherein the method includes performing the logical operation in the memory device at runtime.

6. The method of claim 5, wherein the logical operation is not performed by a host coupled to the memory device.

7. The method of claim 5, wherein the data stored in the physical addresses is not transferred to a host coupled to the memory device for performing the logical operation.

8. The method of claim 1, wherein dereferencing comprises dereferencing with a memory management unit of a host coupled to the memory device.

9. The method of claim 1, wherein dereferencing comprises dereferencing with the memory device.

10. The method of claim 1, wherein the method includes:

compiling the source code to include a reference to the virtual register file for data subject to a memory operation; and

dereferencing the reference at runtime to obtain physical addresses of a memory device element according to the virtual register file.

11. A non-transitory computer readable medium storing instructions executable by a processor to:

define a buffer in host memory with sufficient space to contain backing storage for a virtual register file;

logically split the buffer into virtual vector registers, virtual scalar registers, and virtual control registers, collectively comprising the virtual register file; and

represent a vector register, a scalar register, and a control register with a respective index to the virtual register file at compile time.

12. The medium of claim 11, including instructions to represent the vector register and the virtual scalar register with a respective index to the virtual register file for a fixed amount of the backing storage.

13. The medium of claim 11, including instructions to represent the control register with a respective index to the virtual register file for a variable amount of the backing storage.

14. The medium of claim 11, including instructions to store a base virtual address of a memory device element in the virtual vector register.

15. The medium of claim 14, including instructions to translate the base virtual address to a physical address at runtime.

16. The medium of claim 14, wherein including instructions to store a stride of memory device elements and a length in number of memory device elements in the virtual register file that, together with the translated base virtual address, define which memory device elements correspond to the virtual vector register.

17. The medium of claim 16, including instructions to perform a logical operation, which addresses the index representing the vector register, on data stored in the memory device elements at runtime.

18. A method, comprising:

compiling source code with a host device; and

virtualizing access to a memory device with a virtual register file that stores virtual addresses referenced by indices in the compiled source code; and

initializing a logical operation, according to a portion of the compiled source code, that addresses a particular virtual address,

wherein the logical operation is to be performed in the memory device on data stored in a particular physical addresses corresponding to the particular virtual address.

19. The method of claim 18, wherein compiling source code includes generating compiled code to include the indices for logical operations.

20. The method of claim 19, wherein compiling the source code includes generating the compiled code not to include the particular physical addresses.

21. The method of claim 18, wherein virtualizing access to the memory device comprises targeting the virtual register file as a register for the host device for the logical operation to be performed in the memory device.

22. The method of claim 18, wherein the method includes not storing the particular physical address in the virtual register file.

23. A method, comprising:

running an application on a host;

creating, at runtime, a virtual register file including virtual memory addresses of memory device elements;

loading, at runtime by the application, a library including the virtual register file into main memory of the host; and

translating a particular virtual memory address to a physical address in response to a logical operation to be performed in the memory device.

24. The method of claim 23, wherein the method includes not storing data on which the logical operation is to be performed in the virtual register file and not storing the physical address in the virtual register file.

25. The method of claim 23, wherein translating comprises translating by a memory management unit of the host.

26. The method of claim 23, wherein translating comprises translating by a runtime environment of the memory device.

27. The method of claim 23, wherein the method includes relocating the application in the main memory of the host without editing the virtual register file.

28. An apparatus, comprising:

a host including a processor and main memory; and

a memory device coupled to the host, wherein the host is configured to;

define a buffer in the main memory as a virtual register file that stores virtual addresses of elements of the memory device;

compile source code to target the virtual register file for logical operations to be performed in the memory device as though the logical operations were to be performed in the virtual register file; and

execute the compiled source code to cause the logical operations to be performed in the memory device.

29. The apparatus of claim 28, wherein the host is configured to create the virtual register file at runtime.

30. The apparatus of claim 28, wherein the host includes a memory management unit configured to translate the virtual addresses to physical addresses of the elements of the memory device.

31. The apparatus of claim 28, wherein the virtual register file does not store data corresponding to the elements of the memory device.

32. The apparatus of claim 28, wherein the virtual register file does not store physical addresses of the element of the memory device.