CAPACITY PLANNING FOR SYSTEMS WITH MULTIPROCESSOR BOARDS

• US 20160292318A1
• Filed: 03/31/2015
• Published: 10/06/2016
• Est. Priority Date: 03/31/2015
• Status: Active Grant

• Current Assignee: CA, Inc. (d/b/a CA Technologies) (Broadcom, Inc.)
• Original Assignee: CA, Inc. (d/b/a CA Technologies) (Broadcom, Inc.)
• Inventors: ZINK, Kenneth, NEUSE, Douglas
• Granted Patent: US 10,579,748 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/3442 for planning or managing the needed capacity
• CPC Class Codes: G06F 11/3447 Performance evaluation by modeling
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30

Abstract

Methods of analyzing and capacity planning for multi-core, multi-chip, multi-threaded computer system environments by analyzing the scalability of a fourth layer complexity, the processor boards, and incorporating this factor into the calculation of the expected throughput of a system constructed with multiple processor boards. In particular, the method may comprise identifying a system for which system performance prediction is desired, specifying a simulation model, and determining configuration parameters for the system, the system with at least one processor board, at least one chip per board, at least one core per chip, and at least one thread per core. The method may further comprise obtaining scalability factors based on the configuration data for the system, executing a simulation process for the simulation model for a deterministic simulation time, calculating a throughput of the system as a prediction of the performance of the system, and storing the results in a storage device.

Claims

1. A computer-implemented method, comprising:

identifying a system for which system performance prediction is desired;

specifying a simulation model;

determining configuration parameters for the system, the system comprising at least one processor board, at least one chip per board, at least one core per chip, and at least one thread per core;

obtaining scalability factors based on the configuration data for the system;

executing a simulation process for the simulation model for a deterministic simulation time;

calculating a throughput of the system as a prediction of the performance of the system; and

storing the results in a storage device.

2. The method of claim 1, wherein the simulation model comprises one of:

a discrete event simulation process, and

an analytic simulation process.

3. The method of claim 1, wherein the configuration parameters comprises information including:

a system description,

a processor board type,

a number of processor boards in the system,

a processor chip type,

a number of chips per board,

a number of cores per chip, and

a number of threads per core.

4. The method of claim 1, wherein the step of determining configuration parameters for the system further comprises:

determining a number of processor boards available to run a set of tasks;

determining a number of chips per board for each the processor boards;

determining a number of cores per chip for each of the chips;

determining a number of threads per core for each of the cores; and

determining a total number of available threads.

5. The method of claim 1, wherein the scalability factors include linear scalability factors and exponential scalability factors for each of board scalability, chip scalability, core scalability, and thread scalability.

6. The method of claim 5, wherein the scalability factors are determined by:

determining an amount of work performed by a single thread in a single core in a single chip in a single board of the system comprising a number of N processor boards, where N is an integer greater than or equal to 1;

determining a maximum throughput performance rate associated with a configuration of one or more boards of the system comprising a number of N processor boards, where N is an integer greater than or equal to 1;

determining a plurality of measured throughput performance rates for the system;

determining a fit to a thread scalability;

determining a fit to a core scalability;

determining a fit to a board scalability based on the plurality of measured throughput performance rates;

determining a fit to a chip scalability based on the thread scalability, the core scalability, the board scalability, and the plurality of measured throughput performance rates;

multiplying the thread scalability with the core scalability with the chip scalability with the board scalability for each of the number of N processor boards to produce a plurality of total scalability results, each total scalability result of the plurality of total scalability result associated with each of the number of N processor boards; and

multiplying each of the plurality of total scalability results with the amount of work associated with a single thread in a single core in a single chip in a single board of the system to produce an expected throughput of the system configured with each of the number of N processor boards.

7. A system comprising:

s system performance prediction device configured to;

identify or allow identification of a system for which system performance prediction is desired, and

specify or allow specification of a simulation model;

a system configuration data determining device configured to determine configuration parameters for the system, the system comprising at least one processor board, at least one chip per board, at least one core per chip, and at least one thread per core, and a workload specification;

a scalability factors collecting device configured to obtain scalability factors based on the configuration data for the system;

a simulation execution device configured to execute a simulation process for the simulation model for a deterministic simulation time;

an expected throughput determining device configured to calculate a throughput of the system as a prediction of the performance of the system; and

a results storage device configured to store the results in a storage device.

8. The system of claim 7, wherein the simulation process comprises one of:

a discrete event simulation process, and

an analytic modeling process.

9. The system of claim 7, wherein the configuration parameters comprises information including:

a system description,

a processor board type,

a number of processor boards in the system,

a processor chip type,

a number of chips per board,

a number of cores per chip, and

a number of threads per core.

10. The system of claim 7, wherein the system configuration data determining device is further configured to:

determine a number of processor boards available to run a set of tasks;

determine a number of chips per board for each the processor boards;

determine a number of cores per chip for each of the chips;

determine a number of threads per core for each of the cores; and

determine a total number of available threads; and

determine a workload specification.

11. The system of claim 7, wherein the scalability factors include linear scalability factors and exponential scalability factors for each of board scalability, chip scalability, core scalability, and thread scalability.

12. The system of claim 11, wherein the scalability factors are determined by:

a work determining device configured to determine an amount of work performed by a single thread in a single core in a single chip in a single board of the system comprising a number of N processor boards, where N is an integer greater than or equal to 1;

a work determining device configured to determine a maximum throughput rate associated with a configuration of one or more boards of a system comprising a number of N processor boards, where N is an integer greater than or equal to 1;

a throughput performance determining device configured to determine a plurality of measured throughput performance rates for the system;

a thread scalability determining device configured to determine a fit to a thread scalability;

a core scalability determining device configured to determine a fit to a core scalability;

a board scalability determining device configured to determine a fit to a board scalability based on the plurality of measured throughput performance rates;

a chip scalability determining device configured to determine a fit to a chip scalability based on the thread scalability, the core scalability, the board scalability, and the plurality of measured throughput performance rates;

a total scalability determining device configured to multiply, via the system performance prediction module, the thread scalability with the core scalability with the chip scalability with the board scalability for each of the number of N processor boards to produce a plurality of total scalability results, each total scalability result of the plurality of total scalability result associated with each of the number of N processor boards; and

an expected throughput determining device configured to multiply, via the system performance prediction module, each of the plurality of total scalability results with the amount of work associated with a single thread in a single core in a single chip in a single board of the system to produce an expected throughput of the system for each of the number of N processor boards.

13. A computer program product comprising:

a computer-readable storage medium having computer-readable program code embodied therewith, the computer-readable program code comprising;

computer readable program code configured to

identify or allow identification of a system for which system performance prediction is desired, and

specify or allow specification of a simulation process;

computer readable program code configured to determine configuration parameters for the system, the system comprising at least one processor board, at least one chip per board, at least one core per chip, and at least one thread per core;

computer readable program code configured to obtain scalability factors based on the configuration data for the system;

computer readable program code configured to execute a simulation process for the simulation model for a deterministic simulation time;

computer readable program code configured to calculate a throughput of the system as a prediction of the performance of the system; and

computer readable program code configured to store the results in a storage device.