SEMICONDUCTOR MEMORY DEVICE
5 Assignments
0 Petitions
Accused Products
Abstract
According to one embodiment, a semiconductor memory device includes a memory cell including a variable resistance element, a first circuit including a first resistance element and a first transistor, a first bit line, a second transistor, and a sense circuit. The memory cell and the first circuit are connected to the first bit line. One end and the other end of the second transistor are connected to the first bit line and the sense circuit respectively. During a first operation before reading data of the memory cell a voltage of the first bit line falls to a first voltage and the first and second transistors are turned off in response to a fall of the voltage of the first bit line to the first voltage.
-
Citations
40 Claims
-
1-20. -20. (canceled)
-
21. A semiconductor memory device comprising:
-
a memory cell including a variable resistance element; a first circuit including a first resistance element and a first transistor, one end of the first transistor being connected to one end of the first resistance element; a first bit line connected to the memory cell and the first circuit; a second transistor, one end of the second transistor being connected to the first bit line; a sense circuit connected to the other end of the second transistor, the sense circuit including a first node; and a first logic circuit, a first input terminal of the first logic circuit being connected to the first node, a first signal being input into a second input terminal of the first logic circuit, and an output terminal of the first logic circuit being connected to a gate of the first transistor, wherein; the first signal is set to a first logic level during a first operation before a read operation, and the first signal is set to a second logic level during the read operation, the first logic level being different from the second logic level, and during the first operation, a first voltage is applied to a gate of the second transistor, a voltage of the first bit line falls from a second voltage to a third voltage based on a third logic level signal output from the first logic circuit, and a voltage of the first node changes from a fourth voltage to a fifth voltage in response to the fall of the voltage of the first bit line from the second voltage to the third voltage, and the first logic circuit outputs a fourth logic level signal, the fourth logic level being different from the third logic level. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40)
-
Specification