STRUCTURED INTEGRATED CIRCUIT DEVICE WITH MULTIPLE CONFIGURABLE VIA LAYERS

• US 20160293541A1
• Filed: 04/01/2015
• Published: 10/06/2016
• Est. Priority Date: 04/01/2015
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: eASIC Corporation (Intel Corporation)
• Inventors: ANDREEV, Alexander, SCEPANOVIC, Ranko
• Application Number:
  US14/676,497
• Publication Number:
  US 20160293541A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2027/11888 More than 3 levels of metal
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 27/11807 CMOS gate arrays

Abstract

An integrated circuit may include a multi-layer structure having alternating metal interconnection layers and via layers superimposed on a base layer having electronic components, functional blocks, or both. At least two of the via layers may be customizable and may be used to form customized interconnections that may customize functionality of the resulting integrated circuit. In a variant, at least some of the layers may have a default structure that may result in a default integrated circuit functionality; the default structure may be changed to customize functionality. One or more metal interconnection layers may also be customizable. Additionally, transistors of the base layer may be customized for speed and/or power consumption by adjusting voltage thresholds and/or gate lengths.

Claims

1. An integrated circuit, including:

transistor layers comprising electronic components or functional blocks or both;

a plurality of alternating metal interconnection layers and via layers, superimposed on the transistor layers, and configured to form interconnections among the electronic components or functional blocks or both, wherein the plurality of alternating metal interconnection layers and via layers includes at least two customizable via layers; and

a contact layer disposed between the plurality of alternating metal interconnection layers and via layers and the transistor layers and configured to provide connectivity between the transistor layers and at least one of the plurality of metal interconnection layers.

2. The integrated circuit of claim 1, wherein the interconnections among the electronic components or functional blocks or both include at least one interconnection that is made by a single one of the at least two customizable via layers.

3. The integrated circuit of claim 1, wherein the interconnections among the electronic components or functional blocks or both include at least one interconnection made using at least two of the at least two customizable via layers.

4. The integrated circuit of claim 1, wherein the plurality of alternating metal interconnection layers and via layers further includes at least one customizable metal interconnection layer.

5. The integrated circuit of claim 1, wherein the metal interconnection layers and via layers include one or more default layers configured to provide a default functionality.

6. The integrated circuit of claim 5, wherein one or more of the one or more default layers is a customizable layer.

7. The integrated circuit of claim 1, wherein the contact layer is customizable.

8. The integrated circuit of claim 1, wherein the electronic components, functional blocks, or both of the transistor layers are interconnected by the contact layer and the plurality of alternating metal interconnection layers and via layers to form one or more further functional blocks.

9. The integrated circuit of claim 8, wherein at least one of the one or more further functional blocks is obtained by customizing a different subset of the at least two customizable via layers from a subset of the at least two customizable via layers customized to obtain another further functional block, wherein the different subset may include zero, one, two, or more of the at least two customizable via layers.

10. The integrated circuit of claim 8, wherein different portions of a single further functional block are obtained by customizing different subsets of the at least two customizable via layers.

11. A method of fabricating an integrated circuit, the method including:

forming transistor layers comprising electronic components or functional blocks or both;

forming a contact layer on the transistor layers;

superimposing on the contact layer a plurality of alternating metal interconnection layers and via layers, wherein the contact layer is configured to provide connectivity between the transistor layers and one or more of the metal layers, wherein the plurality of alternating metal interconnection layers and via layers are configured to provide interconnections among the electronic components or functional blocks or both, wherein the plurality of alternating metal interconnection layers and via layers includes at least two customizable via layers, and wherein the superimposing includes forming the at least two customizable via layers according to respective specified customizations.

12. The method of claim 11, wherein at least one of the metal interconnection layers is customizable, and wherein the superimposing further includes forming the at least one customizable metal interconnection layer according to a specified customization.

13. The method of claim 11, wherein forming the at least two customizable via layers includes using a single one of the at least two customizable via layers to provide at least one customized function to the integrated circuit.

14. The method of claim 11, wherein forming the at least two customizable via layers includes using at least two of the at least two customizable via layers to provide at least one customized function to the integrated circuit.

15. The method of claim 11, wherein the superimposing includes creating a default functionality of the integrated circuit.

16. The method of claim 15, further including receiving from a customer a design specification and using the design specification to modify at least one of the at least two customizable via layers from its default state.

17. The method of claim 11, wherein forming the contact layer includes customizing the contact layer.

18. The method of claim 11, wherein the superimposing comprises using a plurality of masks to form the alternating metal interconnection layers and via layers, and wherein the customizing comprises using at least two customized masks to form the at least two customized via layers.

19. The method of claim 18, wherein the superimposing further comprises using at least one customized mask to form at least one customized metal layer.

20. The method of claim 11, wherein the electronic components or functional blocks or both of the transistor layers are interconnected by the contact layer and the plurality of alternating metal interconnection layers and via layers to form one or more further functional blocks.

21. The method of claim 20, wherein at least one of the one or more further functional blocks is obtained by customizing a different subset of the at least two customizable via layers from a subset of the at least two customizable via layers customized to obtain another further functional block, wherein the different subset comprises zero, one, two, or more of the at least two customizable via layers.

22. The integrated circuit of claim 20, wherein different portions of a single further functional block are obtained by customizing different subsets of the at least two customizable via layers.