DIGITAL IMAGING AND PULSE DETECTION PIXEL

• US 20160293647A1
• Filed: 03/30/2015
• Published: 10/06/2016
• Est. Priority Date: 03/30/2015
• Status: Active Grant

• Current Assignee: Hamilton Sundstrand Corporation (Rtx Corporation)
• Original Assignee: Hamilton Sundstrand Corporation (Rtx Corporation)
• Inventors: Lin, Minlong, Lund, Joshua
• Granted Patent: US 9,698,182 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G01S 17/86 Combinations of lidar systems with systems other than lidar, radar or sonar, e.g. with direction finders
• CPC Class Codes: G01S 7/4804 Auxiliary means for detecting or identifying lidar signals or the like, e.g. laser illuminators
• CPC Class Codes: G01S 7/4863 Detector arrays, e.g. charge-transfer gates
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers

Abstract

An imaging and pulse detection array includes: a plurality of pixels connected to a controller, the controller being configured to generate an image based on an image signal originating from each pixel in the plurality of pixels and configured to detect a pulse on at least one of the pixels in the plurality of pixels, and each of the pixels in the plurality of pixels including an imaging circuit and a pulse detection circuit, the imaging circuit and the pulse detection circuit including a shared circuit architecture, and wherein the imaging circuit and the pulse detection circuit include a shared portion.

Claims

1. An imaging and pulse detection array comprising:

a plurality of pixels connected to a controller, the controller being configured to generate an image based on an image signal originating from each pixel in said plurality of pixels and configured to detect a pulse on at least one of said pixels in said plurality of pixels; and

each of said pixels in said plurality of pixels including an imaging circuit and a pulse detection circuit, the imaging circuit and the pulse detection circuit including a shared circuit architecture, and wherein said imaging circuit and said pulse detection circuit include a shared portion.

2. The imaging and pulse detection array of claim 1, wherein the shared portion comprises an optical detection device configured to provide an optical detection input to each of said imaging circuit and said pulse detection circuit.

3. The imaging and pulse detection array of claim 2, wherein the shared portion comprises at least one of an amplifier and a current source connecting the optical detection input to each of said imaging circuit and said pulse detection circuit.

4. The imaging and pulse detection array of claim 2, wherein said optical detection input is a reverse biased light sensing diode.

5. The imaging and pulse detection array of claim 2, wherein said shared portion further comprises a pulse detection output.

6. The imaging and pulse detection array of claim 5, wherein said pulse detection output is connected to a pulse processing circuit within each pixel of said plurality of pixels.

7. The imaging and pulse detection array of claim 6, wherein said pulse processing circuit is a bandwidth-processing circuit including an AC-coupling and high pass filtering process, an asynchronous pulse generation process and a digital pulse detection process.

8. The imaging and pulse detection array of claim 7, wherein said AC-coupling and high pass filtering process is a bandwidth processing process configured to remove frequencies below a pass threshold from the pulse detection output.

9. The imaging and pulse detection array of claim 7, wherein said digital pulse detection process is a bandwidth processing process configured to identify a presence of a pulse on the pulse detection output.

10. The imaging and pulse detection array of claim 7, wherein the asynchronous pulse generation process is a bandwidth processing process configured to reduce a number of pulse detection outputs passed to the controller by the pulse processing circuit.

11. The imaging and pulse detection array of claim 1, wherein each of said imaging circuit and said pulse detection circuit are circuits on a single integrated chip.

12. The imaging and pulse detection array of claim 11, wherein the single integrated chip is a readout integrated circuit (ROIC).

13. The imaging and pulse detection array of claim 1, wherein each of said pixels includes an image output connected to the controller through a capacitive filter.

14. A method for operating a pixel for an imaging and pulse detection array comprising:

detecting a light input at a shared optical detection input and passing said light input through at least one additional shared circuit element;

providing an output from the at least one shared circuit element to an imaging circuit and to a pulse detection circuit, wherein the imaging circuit and the pulse detection circuit share a circuit architecture; and

outputting an imaging signal from the imaging circuit to a controller, and outputting a pulse detection signal from the pulse detection circuit to a pulse processing circuit.

15. The method of claim 14, further comprising processing a pulse detection signal from said pulse detection circuit and passing a pulse detected signal to a controller when a pulse is detected at said shared optical detection input.