Semiconductor Device with Gate Fins

• US 20160293751A1
• Filed: 03/28/2016
• Published: 10/06/2016
• Est. Priority Date: 03/31/2015
• Status: Abandoned Application

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Siemieniec, Ralf, Laforet, David
• Application Number:
  US15/082,214
• Publication Number:
  US 20160293751A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0856 Source regions
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/8613 Mesa PN junction diodes

Abstract

A semiconductor device includes gate fins extending from a first surface into a semiconductor portion. The gate fins include gate electrodes and are arranged along element lines, wherein longitudinal axes of the gate fins are parallel to the element lines. Column sections of the semiconductor portion separate the gate fins from each other along the element lines.

Claims

1. A semiconductor device, comprising:

gate fins comprising gate electrodes and extending from a first surface into a semiconductor portion, wherein the gate fins are arranged along element lines, longitudinal axes of the gate fins are parallel to the element lines, and column sections of the semiconductor portion separate the gate fins from each other along the element lines.

2. The semiconductor device of claim 1, wherein a distance between neighboring gate fins along the element lines is at least 150 nm.

3. The semiconductor device of claim 1, wherein the semiconductor portion comprises one or more body zones forming one or more first pn junctions with a drift structure and second pn junctions with source zones.

4. The semiconductor device of claim 3, wherein each column section comprises a body column portion of the body zones, and wherein each body column portion is completely depletable when a voltage of 0V is applied between the gate electrodes and the source zones.

5. The semiconductor device of claim 1, further comprising:

field electrode structures extending between neighboring first element lines from the first surface into the semiconductor portion and comprising a field dielectric insulating a field electrode from the semiconductor portion.

6. The semiconductor device of claim 5, wherein the field electrode structures are stripe-shaped and run parallel to the element lines.

7. The semiconductor device of claim 5, wherein the field electrodes are spicular and arranged along electrode lines parallel to the element lines.

8. The semiconductor device of claim 1, wherein the element lines are parallel lines.

9. The semiconductor device of claim 1, wherein the element lines are continuous lines.

10. The semiconductor device of claim 1, wherein the element lines are straight lines.

11. The semiconductor device of claim 1, wherein the element lines comprise first element lines and second element lines intersecting the first element lines, the first and second element lines forming a grid.

12. The semiconductor device of claim 11, wherein the grid comprises straight first element lines parallel to each other and straight, parallel second element lines intersecting the first element lines, and wherein the gate fins comprise first gate fins arranged along the first element lines and second gate fins arranged along the second element lines.

13. The semiconductor device of claim 11, wherein the grid comprises continuous zig-zag first element lines and discontinuous parallel second element lines intersecting the first element lines, and wherein the gate fins comprise first gate fins arranged along the first element lines and second gate fins arranged along the second element lines.

14. The semiconductor device of claim 11, wherein the field electrode structures are formed in meshes of the grid.

15. The semiconductor device of claim 11, wherein the column sections are formed at crossings of the first and second element lines.

16. The semiconductor device of claim 11, wherein at least two first gate fins are formed on each first element line per mesh of the grid.

17. The semiconductor device of claim 11, wherein at least two second gate fins are formed on each second element line per mesh of the grid.

18. The semiconductor device of claim 1, further comprising:

a gate wiring outside the semiconductor portion and comprising wiring sections parallel to the element lines; and

gate contacts that extend through a pre-metal dielectric sandwiched between the gate wiring and the semiconductor portion and that electrically connect the gate wiring with the gate electrodes.

19. The semiconductor device of claim 18, further comprising:

a first load electrode outside the semiconductor portion; and

load contact structures that extend through the pre-metal dielectric and an inter-metal dielectric sandwiched between the first load electrode and the gate wiring,

wherein the load contact structures electrically connect the first load electrode with the field electrodes.

20. A semiconductor device, comprising:

first and second gate fins extending from a first surface into a semiconductor portion, wherein the first gate fins are arranged along first element lines and the second gate fins are arranged along second element lines crossing the first element lines, wherein the first and second gate fins comprise gate electrodes and first column sections of the semiconductor portion separate first gate fins from second gate fins at crossings of the first and second element lines; and

field electrode structures extending from the first surface into the semiconductor portion, the field electrode structures comprising a field dielectric insulating spicular field electrodes from the semiconductor portion.

21. The semiconductor device of claim 20, wherein the field electrode structures are formed in meshes of a grid formed by the first and second element lines.

22. The semiconductor device of claim 20, further comprising:

a gate wiring comprising first wiring sections parallel to the first element lines and second wiring sections parallel to the second element lines; and

gate contacts directly connecting the first wiring sections with gate electrodes in the first gate fins and the second wiring sections with gate electrodes in the second gate fins.

23. The semiconductor device of claim 20, further comprising:

a pre-metal dielectric sandwiched between the gate wiring and the semiconductor portion.

24. A method of manufacturing a semiconductor device, the method comprising:

forming gate fins extending from a process surface into a semiconductor layer and arranged along element lines, wherein the gate fins are separated from each other along the element lines by column sections of the semiconductor layer;

forming gate contacts that extend through a pre-metal dielectric formed on the process surface to gate electrodes formed in the gate fins; and

forming a gate wiring on the pre-metal dielectric, the gate wiring connecting the gate contacts.