SEMICONDUCTOR STRUCTURE HAVING A JUNCTION FIELD EFFECT TRANSISTOR AND A HIGH VOLTAGE TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME
First Claim
Patent Images
1. A semiconductor device comprising:
- a high voltage transistor and a junction field effect transistor (JFET) formed on a substrate, whereinthe JFET comprisesa first conductivity type deep-well region comprising a diffusion region located on the substrate,a second conductivity type buried impurity layer located on the deep-well region,a first conductivity type common drain region located on the deep-well region,a first conductivity type first source region located on the deep-well region,a second conductivity type pick-up region formed on the substrate, andan insulating layer formed on the substrate between the first drain region and the first source region, whereinthe diffusion region has an impurity concentration that is lower than other portions of the deep-well region.
3 Assignments
0 Petitions
Accused Products
Abstract
The present examples relate to a junction field effect transistor (JFET) that shares a drain with a high voltage field effect transistor. The present examples are able to control a pinch-off feature of the junction transistor while also maintaining electric features of the high voltage transistor by forming a groove on a lower part of a first conductivity type deep-well region located on a channel region of the junction transistor in a channel width direction.
75 Citations
20 Claims
-
1. A semiconductor device comprising:
-
a high voltage transistor and a junction field effect transistor (JFET) formed on a substrate, wherein the JFET comprises a first conductivity type deep-well region comprising a diffusion region located on the substrate, a second conductivity type buried impurity layer located on the deep-well region, a first conductivity type common drain region located on the deep-well region, a first conductivity type first source region located on the deep-well region, a second conductivity type pick-up region formed on the substrate, and an insulating layer formed on the substrate between the first drain region and the first source region, wherein the diffusion region has an impurity concentration that is lower than other portions of the deep-well region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. A semiconductor device comprising:
-
a first conductivity type deep-well region located on a substrate; a second conductivity type buried impurity layer located on the deep-well region; a first conductivity type first drain region and a first source region located on the deep-well region; a second conductivity type first pick-up region located on the substrate; an insulating layer located on the substrate surface between the first drain region and the first source region; and a junction field effect transistor (JFET) gate region formed on a part of the deep-well region and formed to be in contact with a lower part of the insulating layer and formed to pass through the buried impurity layer. - View Dependent Claims (12, 13, 14, 17)
-
-
15. A semiconductor device comprising:
-
a first conductivity type deep-well region having a first concentration located on a substrate; a first conductivity type semiconductor region having a second concentration that is lower than the first concentration and located in the deep-well region; a second conductivity type impurity layer that is located on the deep-well region; a first conductivity type drain region and a source region that are located separately from the semiconductor region; and a second conductivity type pick-up region located on the substrate, wherein a region of the second conductivity type impurity layer is in contact with the semiconductor region, and a pinch-off voltage is generated through the semiconductor region. - View Dependent Claims (16)
-
-
18. A junction field effect transistor (JFET) comprising:
-
a deep-well region comprising a diffusion region located on a substrate, wherein the JFET also comprises a buried impurity layer, a common drain region, and a first source region located on the deep-well region and a pick-up region and an insulating layer located on the substrate, wherein the insulating layer is located on the substrate between the first drain region and the first source region, and wherein the diffusion region has an impurity concentration that is lower than other portions of the deep-well region. - View Dependent Claims (19, 20)
-
Specification