NONPLANAR III-N TRANSISTORS WITH COMPOSITIONALLY GRADED SEMICONDUCTOR CHANNELS

• US 20160293774A1
• Filed: 06/09/2016
• Published: 10/06/2016
• Est. Priority Date: 12/21/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Then, Han Wui, Dasgupta, Sansaptak, Radosavljevic, Marko, Chu-Kung, Benjamin, Sung, Seung Hoon, Gardner, Sanaz K., Chau, Robert S.
• Granted Patent: US 9,806,203 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02387 Group 13/15 materials
• CPC Class Codes: H01L 21/02389 Nitrides
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/0251 Graded layers
• CPC Class Codes: H01L 21/02538 Group 13/15 materials
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66409 Unipolar field-effect transistors
• CPC Class Codes: H01L 29/66522 with an active layer made of a group 13/15 material H01L29/66446 takes precedence
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/772 Field effect transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78681 having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A III-N semiconductor channel is compositionally graded between a transition layer and a III-N polarization layer. In embodiments, a gate stack is deposited over sidewalls of a fin including the graded III-N semiconductor channel allowing for formation of a transport channel in the III-N semiconductor channel adjacent to at least both sidewall surfaces in response to a gate bias voltage. In embodiments, a gate stack is deposited completely around a nanowire including a III-N semiconductor channel compositionally graded to enable formation of a transport channel in the III-N semiconductor channel adjacent to both the polarization layer and the transition layer in response to a gate bias voltage.

Claims

1. A non-planar III-N transistor disposed above a substrate, the transistor comprising:

a plurality of vertically arranged nanowires, each nanowire comprising two wide band gap material layers on opposing surfaces of a III-N semiconductor material, and each nanowire having a source region, a channel region and a drain region;

a gate stack comprising a gate dielectric and gate electrode, the gate stack surrounding the channel region of each of nanowire, wherein the gate stack is further disposed between the channel regions of vertically adjacent nanowires;

a source contact disposed laterally adjacent to the source region of each nanowire but not between the source regions of vertically adjacent nanowires; and

a drain contact disposed laterally adjacent to the drain region of each nanowire but not between the drain regions of vertically adjacent nanowires.

2. The non-planar III-N transistor of claim 1, further comprising:

a sacrificial material disposed between the source regions of vertically adjacent nanowires and disposed between the drain regions of vertically adjacent nanowires.

3. The non-planar III-N transistor of claim 2, wherein the sacrificial material is further disposed under source and drain regions of a bottommost nanowire of the plurality of vertically arranged nanowires.

4. The non-planar III-N transistor of claim 3, wherein the sacrificial material is further disposed over source and drain regions of an uppermost nanowire of the plurality of vertically arranged nanowires.

5. The non-planar III-N transistor of claim 1, wherein, for each nanowire, the two wide band gap material layers are disposed on vertically opposing surfaces of the III-N semiconductor material.

6. The non-planar III-N transistor of claim 1, wherein, for each nanowire, the two wide band gap material layers are disposed on opposing {0001} surfaces of the III-N semiconductor material.

7. The non-planar III-N transistor of claim 6, wherein the III-N semiconductor material has a compositional grading along a c-axis between the two wide band gap material layers.

8. The III-N transistor of claim 7, wherein the III-N semiconductor material has a band gap that decreases from at least one of the two wide band gap material layers toward a center plane orthogonal to the c-axis and centered within the III-N semiconductor material.

9. The III-N transistor of claim 8, wherein the compositional grading is uniform and symmetric about the center plane.

10. The III-N transistor of claim 9, wherein compositional grading comprises a highest Al content proximate to each of the two wide band gap material layers, decreasing toward the center plane.

11. A method of fabricating a non-planar III-N transistor above a substrate, the method comprising:

forming a fin structure comprising alternating nanowires and sacrificial material layers, each nanowire comprising two wide band gap material layers on opposing surfaces of a III-N semiconductor material, and each nanowire having a source region, a channel region and a drain region;

removing portions of the sacrificial material layers vertically adjacent the channel regions of the nanowires.

forming a gate stack comprising a gate dielectric and gate electrode, the gate stack surrounding the channel region of each of nanowire, wherein the gate stack is further formed between the channel regions of vertically adjacent nanowires;

forming a source contact laterally adjacent to the source region of each nanowire but not between the source regions of vertically adjacent nanowires; and

forming a drain contact laterally adjacent to the drain region of each nanowire but not between the drain regions of vertically adjacent nanowires.

12. The method of claim 11, wherein portions of the sacrificial material layers between the source regions of vertically adjacent nanowires and between the drain regions of vertically adjacent nanowires are not removed.

13. The method of claim 11, wherein portions of the sacrificial material layers under source and drain regions of a bottommost nanowire of the plurality of vertically arranged nanowires are not removed.

14. The method of claim 11, wherein portions of the sacrificial material layers over source and drain regions of an uppermost nanowire of the plurality of vertically arranged nanowires are not removed.

15. The method of claim 11, wherein, for each nanowire, the two wide band gap material layers are formed on vertically opposing surfaces of the III-N semiconductor material.

16. The method of claim 11, wherein, for each nanowire, the two wide band gap material layers are formed on opposing {0001} surfaces of the III-N semiconductor material.

17. The method of claim 16, wherein the III-N semiconductor material has a compositional grading along a c-axis between the two wide band gap material layers.

18. The method of claim 17, wherein the III-N semiconductor material has a band gap that decreases from at least one of the two wide band gap material layers toward a center plane orthogonal to the c-axis and centered within the III-N semiconductor material.

19. The method of claim 18, wherein the compositional grading is uniform and symmetric about the center plane.

20. The method of claim 19, wherein compositional grading comprises a highest Al content proximate to each of the two wide band gap material layers, decreasing toward the center plane.