ELECTRONIC DEVICE HAVING TWO PROCESSORS TO PROCESS DATA

• US 20160295507A1
• Filed: 12/27/2013
• Published: 10/06/2016
• Est. Priority Date: 12/27/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: HUANG, Yuhuan Christina, LU, Jun Feng, SENGUPTA, Uttam K., DING, Ke
• Granted Patent: US 10,721,684 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: H04L 45/22 Alternate routing
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers
• CPC Class Codes: H04W 4/80 Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
• CPC Class Codes: H04W 52/0209 in terminal devices terminal devices per se H04W88/02
• CPC Class Codes: H04W 52/0293 having a sub-controller with a low clock frequency switching on and off a main controller with a high clock frequency
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

An electronic device may be provided that includes a first processor and a second processor, the first processor to wirelessly receive a data packet from another device, and to determine a property (or type) of the received data packet. When the property or type of the received data OTHER DEVICE packet is a first property or first type then the first processor to process the data packet. On the other hand, when the property or type of the received data packet is a second property or second type then the second processor to process the data packet.

Claims

1. An electronic device comprising:

a first processor; and

a second processor, the first processor to wirelessly receive a data packet from another device, and to determine a type of the received data packet, and when the determined type of the received data packet is a first data packet type then the first processor to process the data packet, and when the determined type of the received data packet is a second data packet type then the first processor to provide the data packet to the second processor and the second processor to process the data packet.

2. The electronic device of claim 1, wherein the first processor is a services processing logic.

3. The electronic device of claim 1, wherein the second processor is a host processor.

4. The electronic device of claim 1, wherein when the determined type of the received data packet is the second data packet type, the first processor to wake up the second processor and to forward the data packet to the first processor.

5. The electronic device of claim 1, wherein the first processor to determine the type of the received data packet based on a header of the data packet.

6. The electronic device of claim 1, wherein the first processor and the second processor to be provided on a silicon chip.

7. The electronic device of claim 1, wherein the first processor to include a first software stack, and the second processor to include a second software stack.

8. The electronic device of claim 7, wherein the first software stack to include profile information related to the first data packet type, and the second software stack to include profile information related to the second data packet type.

9. An apparatus comprising:

logic, at least a portion of which is hardware, to receive a data packet and to determine a type of the data packet, the logic to process the data packet by a first processor when the data packet is determined to be a first data packet type, and the logic to forward the data packet to a second processor when the data packet is determined to be a second data packet type, and the second processor to process the forwarded data packet.

10. The apparatus of claim 9, wherein the first processor is a services processing logic.

11. The apparatus of claim 9, wherein the second processor is a host processor.

12. The apparatus of claim 9, wherein when the determined type of the received data packet is the second data packet type, the first processor to wake up the second processor and to forward the data packet to the second processor.

13. The apparatus of claim 9, wherein the logic to be provided on a silicon chip.

14. The apparatus of claim 9, wherein the first processor to include a first software stack, and the second processor to include a second software stack.

15. The apparatus of claim 14, wherein the first software stack to include profile information related to the first data packet type, and the second software stack to include profile information related to the second data packet type.

16. A method of an electronic device, comprising:

receiving a data packet at a first processor;

determining a type of the received data packet;

processing the data packet at the first processor when the received data packet is determined to be a first data packet type;

providing the data packet to a second processor when the received data packet is determined to be a second data packet type; and

processing the data packet at the second processor.

19. The method of claim 16, wherein providing the data packet to the second processor includes waking up the second processor and forwarding the data packet to the first processor.

20. The method of claim 16, wherein determining the type of the received data packet includes determining the type of the data packet based on a header of the data packet.

21. The method of claim 16, wherein the first processor and the second processor to be provided on a silicon chip.

22. The method of claim 16, wherein the first processor to include a first software stack, and the second processor to include a second software stack, the first software stack to include profile information related to the first data packet type, and the second software stack to include profile information related to the second data packet type.

17. (canceled)

18. (canceled)

23. (canceled)

24. A machine readable medium comprising one or more instructions that when executed cause a first processor and a second processor to perform one or more operations to:

determine a type of a data packet received at the first processor;

process the data packet at the first processor when the received data packet is determined to be a first data packet type;

provide the data packet to a second processor when the received data packet is determined to be a second data packet type; and

process the data packet at the second processor.

25. The machine readable medium of claim 24, wherein providing the data packet to the second processor includes waking up the second processor and forwarding the data packet to the first processor.

26. The machine readable medium of claim 24, wherein determining the type of the received data packet includes determining the type of the data packet based on a header of the data packet.

27. The machine readable medium of claim 24, wherein the first processor and the second processor to be provided on a silicon chip.

28. The machine readable medium of claim 24, wherein the first processor to include a first software stack, and the second processor to include a second software stack, the first software stack to include profile information related to the first data packet type, and the second software stack to include profile information related to the second data packet type.

29. (canceled)