STT-MRAM Bitcell for Embedded Flash Applications

• US 20160300604A1
• Filed: 04/11/2016
• Published: 10/13/2016
• Est. Priority Date: 04/10/2015
• Status: Active Grant

• Current Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Original Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Inventors: WONG, Jack Tim, LEE, Kangho, TOH, Eng Huat, QUEK, Elgin Kiok Boone
• Granted Patent: US 9,653,137 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/1655 Bit-line or column circuits
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type

Abstract

A spin transfer torque magnetic random access memory (STT-MRAM) device and a method to perform operations of an embedded eFlash device are disclosed. The STT-MRAM device is configured to include an array of STT-MRAM bitcells. The array includes a plurality of bitlines (BLs) and a plurality of word lines (WLs), where the bitlines form columns and the wordlines form rows of STT-MRAM bitcells. Each STT-MRAM bitcell includes a magnetic tunnel junction (MTJ) element coupled in series to an access transistor having a gate terminal and source and drain terminals. The array includes a plurality of source lines (SLs) coupled to the source terminals of the access transistors. A SL of the plurality of SLs is coupled to source terminals of access transistors of two or more adjacent columns of the STT-MRAM cells. The shared SL is parallel to the plurality of BLs. The operations of such a STT-MRAM bitcell are configured to include: an initialization operation, a program operation, and a sector erase operation.

Claims

1. A spin transfer torque magnetic random access memory (STT-MRAM) device comprising:

a first bitline having M number of STT-MRAM cells,

a second bitline having M number of STT-MRAM cells, wherein

the first and second bitlines form first and second columns of STT-MRAM cells, and a MRAM cell comprises

a magnetic tunnel junction (MTJ) element having first and second MTJ terminals, and

an access transistor having a gate, source and drain terminals, wherein the drain terminal is coupled the first MTJ terminal, providing a series coupling

between the access transistor with the MTJ element;

a plurality of M number of word lines (WLs) coupled to the gate terminals of the access transistors of the STT-MRAM cells, wherein a WL is coupled to one STT-MRAM cell in the first and second bitlines to form a row of STT-MRAM cells, the plurality of M number of WLs form M rows of STT-MRAM cells; and

a source line (SL) coupled to the source terminals of the access transistors of the STT-MRAM cells of the first and second columns of STT-MRAM cells, wherein the SL is shared by the first and second columns of STT-MRAM cells.

2. The STT-MRAM device of claim 1 wherein the SL is configured to be parallel to the first and second bitlines.

3. The STT-MRAM device of claim 2 wherein the first and second columns of STT-MRAM cells form a pair of columns of STT-MRAM cells with a shared SL.

4. The STT-MRAM device of claim 2 wherein during a sector erase operation, the shared SL is driven by suitable voltage while the first and second bitlines are grounded to erase all the STT-MRAM cells sharing the SL as in an eFlash erase operation.

5. The STT-MRAM device of claim 2, wherein during a program operation, one of the first and second bitlines is driven by suitable voltage while the shared SL is grounded to allow for selectively writing a logical H value to a randomly accessible STT-MRAM cell as in an eFlash program operation.

6. A spin transfer torque magnetic random access memory (STT-MRAM) device having an array of STT-MRAM cells configured as an embedded Flash (eFlash) replacement device, the array comprises:

a plurality of N number of bitlines having M number of MRAM cells, the bitlines forming N columns of MRAM cells, wherein each MRAM cell comprises

a magnetic tunnel junction (MTJ) element having first and second MTJ terminals, and

an access transistor having a gate and source and drain terminals, wherein the drain terminal is coupled the first MTJ terminal, providing a series coupling between the access transistor with the MTJ element;

a plurality of M number of word lines (WLs) coupled to the gate terminals of the access transistors of the STT-MRAM cells of the array, wherein a WL is coupled to one STT-MRAM cell in each of the N bitlines to form a row of STT-MRAM cells, the plurality of M number of WLs form M rows of STT-MRAM cells; and

a plurality of S number of source lines (SLs) coupled to source terminals of the access transistors, wherein a SL of the S number of SLs is shared by or coupled to source terminals of access transistors of two or more adjacent columns of the N columns of STT-MRAM cells.

7. The STT-MRAM device of claim 6 wherein the SL is configured to be parallel to the bitlines.

8. The STT-MRAM device of claim 6 wherein N is an even number and S is equal to N/2.

9. The STT-MRAM device of claim 6 wherein the source terminals of adjacent access transistors of the same BL are a common source terminal to form a pair of STT-MRAM cells of a bitline.

10. The STT-MRAM device of claim 9 wherein M is an even number and a bitline has M/2 STT-MRAM cell pairs.

11. The STT-MRAM device of claim 6, wherein during a program operation, a bitline of N number of bitlines is driven by suitable voltage while the shared SL is grounded to allow for selectively writing a logical L value to a randomly accessible STT-MRAM cell of the array as in an eFlash program operation.

12. The STT-MRAM device of claim 11, wherein a uni-directional current is used to perform the program operation.

13. The STT-MRAM device of claim 6 wherein during a sector erase operation, the shared SL is driven by suitable voltage while the bitlines are grounded to erase all the STT-MRAM cells sharing the SL as in an eFlash erase operation.

14. The STT-MRAM device of claim 13 where the STT-MRAM cells sharing the SL are erased and reset to a logical L value during the sector erase operation.

15. The STT-MRAM device of claim 14, wherein the sector erase operation is enabled by asserting the WL in sequence for each WL included in the sector.

16. The STT-MRAM device of claim 6, wherein during an initialization operation, the S number of SLs are driven by suitable voltage while the N number of bitlines are grounded to allow for writing a logical H value to each STT-MRAM cell in the array.

17. The STT-MRAM device of claim 6, wherein a width of the SL is effectively multiplied by shared number of STT-MRAM cells with each SL.

18. The STT-MRAM device of claim 6, wherein the S number of SLs are configured at a metal level greater than metal level M1 to accommodate an increase in the width.

19. A method of forming a spin transfer torque magnetic random access memory (STT-MRAM) device comprising:

forming an array of STT-MRAM cells configured as an embedded Flash (eFlash) replacement device, wherein forming the array comprises

forming a plurality of N number of bitlines having M number of MRAM cells, the bitlines forming N columns of MRAM cells, wherein each MRAM cell comprises

a magnetic tunnel junction (MTJ) element having first and second MTJ terminals, and

an access transistor having a gate and source and drain terminals, wherein the drain terminal is coupled the first MTJ terminal, providing a series coupling between the access transistor with the MTJ element,

forming a plurality of M number of word lines (WLs) coupled to the gate terminals of the access transistors of the STT-MRAM cells of the array, wherein a WL is coupled to one STT-MRAM cell in each of the N bitlines to form a row of STT-MRAM cells, the plurality of M number of WLs form M rows of STT-MRAM cells, and

forming a plurality of S number of source lines (SLs) coupled to source terminals of the access transistors, wherein a SL of the S number of SLs is shared by or coupled to source terminals of access transistors of two or more adjacent columns of the N columns of STT-MRAM cells.

20. The method of claim 19 wherein the S number of SLs are configured to be parallel to the N number of bitlines.