Double-Sided Semiconductor Package and Dual-Mold Method of Making Same

• US 20160300797A1
• Filed: 04/01/2016
• Published: 10/13/2016
• Est. Priority Date: 04/09/2015
• Status: Active Grant

• Current Assignee: Stats Chippac Limited
• Original Assignee: Stats Chippac Limited
• Inventors: Shim, Il Kwon, Marimuthu, Pandi C., Lin, Yaojian
• Granted Patent: US 9,893,017 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/24195 the item being a discrete passive component
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/2929 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/2939 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 : the item being metallic
• CPC Class Codes: H01L 2224/45147 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73227 : Wire and HDI connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/83 : using a layer connector
• CPC Class Codes: H01L 2224/83005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/83192 : wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/85 : using a wire connector
• CPC Class Codes: H01L 2224/85005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/92164 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/92244 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/92247 : the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1041 : Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A semiconductor device comprises a first conductive layer formed on a carrier over an insulating layer. A portion of the insulating layer is removed prior to forming the first conductive layer. A first semiconductor die is disposed over the first conductive layer. A discrete electrical component is disposed over the first conductive layer adjacent to the first semiconductor die. A first encapsulant is deposited over the first conductive layer and first semiconductor layer. A conductive pillar is formed through the first encapsulant between the first conductive layer and second conductive layer. A second encapsulant is deposited around the first encapsulant, first conductive layer, and first semiconductor die. A second conductive layer is formed over the first semiconductor die, first encapsulant, and second encapsulant opposite the first conductive layer. The carrier is removed after forming the second conductive layer. A semiconductor package is mounted to the first conductive layer.

Claims

1. A method of making a semiconductor device, comprising:

forming a first conductive layer;

disposing a first semiconductor die over the first conductive layer;

depositing a first encapsulant over the first conductive layer and first semiconductor die;

depositing a second encapsulant around the first encapsulant, first conductive layer, and first semiconductor die; and

forming a second conductive layer over the first semiconductor die, first encapsulant, and second encapsulant opposite the first conductive layer.

2. The method of claim 1, further including:

forming the first conductive layer on a carrier; and

removing the carrier after forming the second conductive layer.

3. The method of claim 1, further including forming the first conductive layer over an insulating layer.

4. The method of claim 3, further including removing a portion of the insulating layer prior to forming the first conductive layer.

5. The method of claim 1, further including disposing a discrete electrical component over the first conductive layer adjacent to the first semiconductor die.

6. The method of claim 1, further including forming a conductive pillar through the first encapsulant between the first conductive layer and second conductive layer.

7. The method of claim 1, further including mounting a semiconductor package to the first conductive layer.

8. A method of making a semiconductor device, comprising:

providing a first semiconductor die;

depositing a first encapsulant around first semiconductor die;

depositing a second encapsulant around the first encapsulant and first semiconductor die; and

forming an interconnect structure over the first semiconductor die, first encapsulant, and second encapsulant.

9. The method of claim 8, further including:

forming a conductive layer over the first semiconductor die opposite the interconnect structure; and

depositing the second encapsulant around the conductive layer.

10. The method of claim 9, further including forming a bond wire to couple the first semiconductor die to the conductive layer.

11. The method of claim 9, further including forming an integrated passive device (IPD) to include a portion of the conductive layer.

12. The method of claim 9, further including disposing a second semiconductor die over the first semiconductor die and electrically connected to the interconnect structure through the conductive layer.

13. The method of claim 8, further including forming a conductive pillar through the first encapsulant.

14. The method of claim 8, further including forming a conductive pillar over the first semiconductor die prior to depositing the first encapsulant.

15. A method of making a semiconductor device, comprising:

providing a first semiconductor die;

depositing a first encapsulant around first semiconductor die; and

depositing a second encapsulant around the first encapsulant and first semiconductor die.

16. The method of claim 15, further including:

disposing the first semiconductor die on a substrate prior to depositing the first encapsulant; and

depositing the second encapsulant over the substrate opposite the first semiconductor die.

17. The method of claim 16, further including:

forming an insulating layer on the substrate; and

disposing the first semiconductor die over the insulating layer, wherein the insulating layer includes glass fibers or cloth.

18. The method of claim 15, further including:

forming a first conductive layer over the first semiconductor die; and

depositing the second encapsulant around the first conductive layer.

19. The method of claim 15, further including forming an interconnect structure over the first semiconductor die, first encapsulant, and second encapsulant.

20. The method of claim 15, further including forming a conductive pillar over the first semiconductor die prior to depositing the first encapsulant.

21. A semiconductor device, comprising:

a first semiconductor die;

a first conductive layer formed over the first semiconductor die;

a first encapsulant deposited around the first semiconductor die and over first conductive layer; and

a second encapsulant deposited around the first encapsulant, first semiconductor die, and first conductive layer.

22. The semiconductor device of claim 21, wherein the second encapsulant surrounds the first encapsulant, first conductive layer, and first semiconductor die.

23. The semiconductor device of claim 21, further including a second conductive layer formed over the first encapsulant and second encapsulant opposite the first semiconductor die.

24. The semiconductor device of claim 23, further including a conductive pillar disposed through the first encapsulant and coupled between the first conductive layer and second conductive layer.

25. The semiconductor device of claim 21, further including a second semiconductor die disposed over the first semiconductor die and coupled to the first semiconductor die through the first conductive layer.