HYBRID HIGH-K FIRST AND HIGH-K LAST REPLACEMENT GATE PROCESS
First Claim
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1. An integrated circuit, comprising:
- an NMOS transistor with a first gate dielectric stack comprised of a high-k first dielectric deposited on a high quality gate dielectric thermally grown at a temperature greater than 850°
C.; and
a PMOS transistor with a second gate dielectric stack comprised of a high-k last gate dielectric deposited on a chemically grown gate dielectric.
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Abstract
An integrated circuit and method with a metal gate NMOS transistor with a high-k first gate dielectric on a high quality thermally grown interface dielectric and with a metal gate PMOS transistor with a high-k last gate dielectric on a chemically grown interface dielectric.
3 Citations
14 Claims
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1. An integrated circuit, comprising:
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an NMOS transistor with a first gate dielectric stack comprised of a high-k first dielectric deposited on a high quality gate dielectric thermally grown at a temperature greater than 850°
C.; anda PMOS transistor with a second gate dielectric stack comprised of a high-k last gate dielectric deposited on a chemically grown gate dielectric. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A process of forming an integrated circuit, comprising the steps:
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providing a partially processed wafer of the integrated circuit; growing a high quality first gate dielectric on the partially processed wafer at a temperature of 850°
C. or greater;depositing a high-k first gate dielectric on the high quality first gate dielectric; forming an NMOS polysilicon replacement gate of an NMOS transistor on the high-k first gate dielectic; forming a PMOS polysilicon replacement gate of a PMOS transistor on the high-k first gate dielectric; depositing a premetal dielectric over the NMOS transistor and over the PMOS transistor; planarizing the premetal dielectric to expose a top of the PMOS polysilicon replacement gate and a top of the NMOS polysilicon replacement gate; removing the NMOS polysilicon replacement gate forming an NMOS replacement gate trench; removing the PMOS polysilicon replacement gate forming a PMOS replacement gate trench; forming an NMOS transistor photo resist pattern wherein the NMOS transistor photo resist pattern covers the NMOS replacement gate trench and exposes the PMOS replacement gate trench; removing the high-k first gate dielectric and removing the high quality first gate dielectric from a bottom of the PMOS replacement gate trench; removing the NMOS transistor photo resist pattern; forming a second gate dielectric layer on the integrated circuit wherein the second gate dielectric covers the bottom of the PMOS replacement gate trench; depositing a high-k last gate dielectric on the integrated circuit; depositing PMOS metal gate material; forming a PMOS transistor photo resist pattern wherein the PMOS photo resist pattern covers the PMOS transistor and exposes the NMOS transistor; etching the PMOS metal gate material from the NMOS transistor; etching the high-k last gate dielectric layer from the NMOS transistor; depositing NMOS metal gate material on the integrated circuit and into the NMOS replacement gate trench; and polishing the integrated circuit to remove the NMOS and the PMOS metal gate material from a surface of the premetal dielectric and to form an NMOS metal gate in the NMOS replacement gate trench and to form a PMOS metal gate in the PMOS replacement gate trench. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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Specification