SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

• US 20160300942A1
• Filed: 05/05/2015
• Published: 10/13/2016
• Est. Priority Date: 04/07/2015
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Feng, Li-Wei, Tsai, Shih-Hung, Lin, Chao-Hung, Hsu, Chih-Kai, Hung, Yu-Hsiang, Jenq, Jyh-Shyang
• Granted Patent: US 9,947,792 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66803 with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first fin-shaped structure thereon; forming a spacer adjacent to the first fin-shaped structure; using the spacer as mask to remove part of the substrate for forming a second fin-shaped structure, in which the second fin-shaped structure comprises a top portion and a bottom portion; and forming a doped portion in the bottom portion of the second fin-shaped structure.

Claims

1. A method for fabricating semiconductor device, comprising:

providing a substrate having a first fin-shaped structure thereon;

forming a spacer adjacent to the first fin-shaped structure;

using the spacer as mask to remove part of the substrate for forming a second fin-shaped structure, wherein the second fin-shaped structure comprises a top portion and a bottom portion; and

forming a doped portion in the bottom portion of the second fin-shaped structure.

2. The method of claim 1, wherein the first fin-shaped structure comprises a mask layer thereon, the method comprises:

using the mask layer and the spacer as mask to remove part of the substrate for forming the second fin-shaped structure.

3. The method of claim 2, further comprising:

forming a liner on the bottom portion of the second fin-shaped structure;

forming a doped layer on the substrate, the liner, the spacer, and the mask layer; and

forming a hard mask on the doped layer.

4. The method of claim 3, wherein the liner comprises silicon oxide.

5. The method of claim 3, wherein the doped layer comprises borosilicate glass (BSG) or phosphosilicate glass (PSG).

6. The method of claim 3, further comprising:

performing an annealing process after forming the hard mask to form the doped region in the bottom portion of the second fin-shaped structure; and

removing the hard mask, the doped layer, and the spacer.

7. A semiconductor device, comprising:

a substrate; and

a fin-shaped structure having a top portion and a bottom portion on the substrate, wherein the top portion and the bottom portion comprise a step-shaped profile therebetween.

8. The semiconductor device of claim 7, wherein the top portion comprises a top surface and a bottom surface, the bottom portion comprises a top surface and a bottom surface, and the width of the bottom surface of the top portion is less than the width of the top surface of the bottom portion.

9. The semiconductor device of claim 8, wherein the sidewalls of the top portion and the top surface of the bottom portion comprise the step-shaped profile therebetween.

10. The semiconductor device of claim 7, wherein the bottom portion comprises a slanted sidewall.

11. A semiconductor device, comprising:

a substrate;

a fin-shaped structure having a top portion and a bottom portion on the substrate; and

a doped region in the bottom portion of the fin-shaped structure, wherein the doped region comprises a v-shaped profile.

12. The semiconductor device of claim 11, wherein the doped region comprises boron or phosphorus.