Wafer Level Packaging of Electronic Devices

• US 20160300991A1
• Filed: 06/21/2016
• Published: 10/13/2016
• Est. Priority Date: 09/20/2009
• Status: Active Grant

• Current Assignee: LED Wafer Solutions LLC
• Original Assignee: Viagan Limited
• Inventors: Margalit, Mordehai, Petronius, Israel
• Granted Patent: US 10,446,726 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/1461 MEMS
• CPC Class Codes: H01L 2933/0066 relating to arrangements for conducting electric current to or from the semiconductor body
• CPC Class Codes: H01L 33/382 the electrode extending partially in or entirely through the semiconductor body
• CPC Class Codes: H01L 33/483 Containers
• CPC Class Codes: H01L 33/486 adapted for surface mounting
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

Aspects of the invention are directed to an electronic device package including an electronic device comprising a first contact point; a metal pad disposed to provide electrical connection to the first contact point; a substrate comprising a first face and a second face opposing the first face of the substrate, the first face of the substrate adjacent a face of the electronic device; and a VIA passing through the substrate from the second face of the substrate to the metal pad, the VIA exhibiting: a pass through extending through the substrate from the first face to the second face; a metal layer disposed within the pass through arranged to provide electrical connectivity to the metal pad from an area adjacent the second face of the substrate; and an electrically insulating first passivation layer disposed between the metal layer and the substrate arranged to provide electrical insulation between the substrate and the metal layer.

Claims

1. A wafer level packaging of semiconductor devices comprising of:

a semiconductor device with a top face and bottom face and at least one metal pad located on bottom face and;

a top cover layer affixed to top face of semiconductor device and;

a bottom cover wafer affixed to bottom face of semiconductor device;

wherein

the bottom cover wafer has at least one via extending from external face of bottom wafer to internal face of said bottom wafer; and

an electroplated metal layer extends from the external face of bottom wafer through the via to the metal pad.

2. The wafer level packaging of semiconductor devices as claimed in claim 1 wherein at least one metal pad is an electrically conducting pad.

3. The wafer level packaging of semiconductor devices as claimed in claim 1 wherein at least one metal pad is a thermally conducting pad.

4. The wafer level packaging of semiconductor devices as claimed in claim 1 wherein the top cover layer is one of a Glass, Quartz, Silicone, Phosphor embedded in a Silicone matrix.

5. The wafer level packaging of semiconductor devices as claimed in claim 1 wherein the bottom cover layer is one of a Silicone, Aluminum Nitride, Aluminum Oxide, polymer, epoxy, Silicone, Solder mask material, Ceramic, Copper, Aluminum.

6. The wafer level packaging of semiconductor devices as claimed in claim 1 wherein the bottom cover wafer has an electrically isolating layer on at least one side of the wafer, said electrically isolating layer can be one of a group of electrically isolating layers consisting of;

Silicon dioxide, Silicon Nitride, Epoxy, Silicone, Polyamide.

7. The wafer level packaging of semiconductor devices as claimed in claim 1 wherein at least one via has an electrically isolating layer on the side wall of the via electrically isolating the electroplated metal layer from the cover wafer, said electrically isolating layer can be one of;

Silicon dioxide, Silicon Nitride, Epoxy, Silicone, Polyamide.

8. The wafer level packaging of semiconductor devices as claimed in claim 1 wherein the semiconductor device is one of;

Light Emitting Diode, photo detector, MEMs.

9. The wafer level packaging of semiconductor devices as claimed in claim 1 wherein the electroplated metal is one of;

Copper, Nickel, Gold, Aluminum or compositions containing these metals.

10. A method of wafer level packaging of semiconductor devices comprising:

attaching multiple semiconductor devices with metal pads to bottom wafer;

applying an encapsulation layer on top of the devices and bottom wafer;

making via holes in bottom cover wafer from the external surface of the wafer to the metal pads; and

electroplating a metal layer to connect the semiconductor device metal pad, through the via to the external face of the wafer.