LIQUID CRYSTAL PANEL AND ACTIVE MATRIX SUBSTRATE USED THEREFOR

• US 20160306247A1
• Filed: 11/28/2014
• Published: 10/20/2016
• Est. Priority Date: 12/02/2013
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: ITO, Kazuatsu, MIYAMOTO, Tadayoshi, UCHIDA, Seiichi
• Granted Patent: US 9,933,676 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G02F 1/133388 with constructional differences between the display region and the peripheral region
• CPC Class Codes: G02F 1/1339 Gaskets; Spacers; Sealing of cells
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: G02F 2202/10 semiconductor
• CPC Class Codes: G09G 2320/0219 Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence

Abstract

A liquid crystal panel (100) includes a pair of substrates (10, 30); a liquid crystal layer (40) provided between the pair of substrates; and a sealing member (42) provided so as to surround the liquid crystal layer. A plurality of pixels (P1, P2) are provided in a matrix in a region surrounded by the sealing member. Each of the plurality of pixels includes an oxide semiconductor TFT (5) provided in one substrate (10) of the pair of substrates; and a pixel electrode (19) provided in the one substrate and connected with the oxide semiconductor TFT. Each of the plurality of pixels is configured such that when the oxide semiconductor TFT is switched from an on-state to an off-state, a level of a voltage to be applied to the liquid crystal layer by use of the pixel electrode is shifted in a negative direction by a pull-in voltage ΔVd. A pull-in voltage ΔVd1 in a first pixel (P1) among the plurality of pixels is lower than a pull-in voltage ΔVd2 in a second pixel (P2) located farther from the sealing member than the first pixel.

Claims

1. A liquid crystal panel, comprising:

a pair of substrates;

a liquid crystal layer provided between the pair of substrates; and

a sealing member provided between the pair of substrates so as to surround the liquid crystal layer;

the liquid crystal panel including a plurality of pixels provided in a matrix in a region surrounded by the sealing member;

wherein;

each of the plurality of pixels includes;

an oxide semiconductor TFT provided in one substrate of the pair of substrates; and

a pixel electrode provided in the one substrate and connected with the oxide semiconductor TFT;

the each of the plurality of pixels is configured such that when the oxide semiconductor TFT is switched from an on-state to an off-state, a level of a voltage to be applied to the liquid crystal layer by use of the pixel electrode is shifted in a negative direction by a pull-in voltage Δ

Vd; and

a pull-in voltage Δ

Vd1 in a first pixel among the plurality of pixels is lower than a pull-in voltage Δ

Vd2 in a second pixel located farther from the sealing member than the first pixel.

2. The liquid crystal panel according to claim 1, further comprising:

a first gate line connected with the first pixel, and a first adjacent gate line connected with a pixel adjacent to the first pixel and extending parallel to the first gate line; and

a second gate line connected with the second pixel, and a second adjacent gate line connected with a pixel adjacent to the second pixel and extending parallel to the second gate line;

wherein an overlapping area of the pixel electrode of the first pixel and the first adjacent gate line is smaller than an overlapping area of the pixel electrode of the second pixel and the second adjacent gate line.

3. The liquid crystal panel according to claim 1, wherein the oxide semiconductor TFT included in the first pixel includes a channel having a width smaller than a width of a channel of the oxide semiconductor TFT included in the second pixel.

4. The liquid crystal panel according to claim 1, wherein a storage capacitance provided in the first pixel is larger than a storage capacitance of the second pixel.

5. The liquid crystal panel according to claim 1, wherein the first pixel is located near the sealing member, and the second pixel is located in a central area of the region surrounded by the sealing member.

6. The liquid crystal panel according to claim 1, comprising a third pixel located between the first pixel and the second pixel, wherein a pull-in voltage Δ

Vd3 in the third pixel is higher than the pull-in voltage Δ

Vd1 in the first pixel and is lower than the pull-in voltage Δ

Vd2 in the second pixel.

7. The liquid crystal panel according to claim 1, wherein the oxide semiconductor layer includes an In—

Ga—

Zn-O-based semiconductor layer.

8. The liquid crystal panel according to claim 7, wherein the In—

Ga—

Zn—

O-based semiconductor layer includes a crystalline portion.

9. An active matrix substrate usable in the liquid crystal panel according to claim 1, the active matrix substrate being the one substrate including the oxide semiconductor TFT and the pixel electrode.