MAP RECYCLING ACCELERATION

• US 20160306577A1
• Filed: 06/29/2016
• Published: 10/20/2016
• Est. Priority Date: 06/25/2013
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Canepa, Timothy, Baryudin, Leonid, Hanna, Stephen D., Tang, Alex G.
• Granted Patent: US 10,303,598 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/214 Solid state disk
• CPC Class Codes: G06F 2212/281 Single cache
• CPC Class Codes: G06F 2212/312 In storage controller
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 3/0608 Saving storage space on storage systems
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

An apparatus includes a memory and a controller. The memory may be configured to store data. The controller may be configured to process a plurality of input/output requests to read/write to/from the memory. The controller generally includes a processor, a cache and a hardware assist circuit. The processor may be configured to initiate a recycle operation by generation of a start index. The cache may be configured to buffer a first level of a map and less than all of a second level of the map. The hardware assist circuit may be configured to search through the first level or any portions of the second level of the map in the cache in response to the start index, and notify the processor in response to the search detecting one or more blocks in the memory that contain valid data to be recycled.

Claims

1. An apparatus comprising:

a memory configured to store data; and

a controller configured to process a plurality of input/output requests to read/write to/from the memory, the controller comprising a processor configured to initiate a recycle operation by generation of a start index, a cache configured to buffer a first level of a map and less than all of a second level of the map, and a hardware assist circuit configured to search through the first level or any portions of the second level of the map in the cache in response to the start index, and notify the processor in response to the search detecting one or more blocks in the memory that contain valid data to be recycled.

2. The apparatus according to claim 1, wherein the valid data includes map data to be recycled in response to the notification.

3. The apparatus according to claim 2, wherein the map data to be recycled is from the second level of the map.

4. The apparatus according to claim 2, wherein the map data to be recycled is from a third level of the map.

5. The apparatus according to claim 1, wherein the hardware assist circuit is implemented solely in dedicated hardware.

6. The apparatus according to claim 1, wherein the hardware assist circuit is further configured to lock one or more slots in the cache that buffer one or more pages of the second level in the map during the recycle operation.

7. The apparatus according to claim 1, wherein the hardware assist circuit is further configured to suspend the recycle operation while servicing a new command to access the memory.

8. The apparatus according to claim 1, wherein the processor is further configured to update one or more pages of the second level in the cache in response to the recycle operation, and copy the one or more pages of the second level as updated from the cache to the memory.

9. The apparatus according to claim 1, wherein the memory and the controller form part of a solid-state drive.

10. A method for map recycling acceleration, comprising the steps of:

processing a plurality of input/output requests to read/write to/from a memory;

initiating a recycle operation by generation of a start index using a processor;

buffering a first level of a map and less than all of a second level of the map in a cache;

searching through the first level or any portions of the second level of the map in the cache using a hardware assist circuit in response to the start index; and

notifying the processor in response to the search detecting one or more blocks in the memory that contain valid data to be recycled.

11. The method according to claim 10, wherein the valid data includes map data to be recycled in response to the notification.

12. The method according to claim 11, wherein the map data to be recycled is from the second level of the map.

13. The method according to claim 11, wherein the map data to be recycled is from a third level of the map.

14. The method according to claim 10, wherein the searching is implemented solely in dedicated hardware.

15. The method according to claim 10, further comprising the step of:

locking one or more slots in the cache that buffer one or more pages of the second level in the map during the recycle operation.

16. The method according to claim 10, further comprising the step of:

suspending the recycle operation while servicing a new command to access the memory.

17. The method according to claim 10, further comprising the steps of:

updating one or more pages of the second level in the cache in response to the recycle operation; and

copying the one or more pages of the second level as updated from the cache to the memory.

18. The method according to claim 10, wherein the steps are performed in a solid-state drive.

19. An apparatus comprising:

an interface configured to process a plurality of read/write operations to/from a memory; and

a control circuit comprising a processor configured to initiate a recycle operation by generation of a start index, a cache configured to buffer a first level of a map and less than all of a second level of the map, and a hardware assist circuit configured to search through the first level or any portions of the second level of the map in the cache in response to the start index, and notify the processor in response to the search detecting one or more blocks in the memory that contain valid data to be recycled.

20. The apparatus according to claim 19, wherein the interface and the control circuit form part of a solid-state drive controller.