GOA Circuit and Liquid Crystal Display

• US 20160307531A1
• Filed: 04/30/2015
• Published: 10/20/2016
• Est. Priority Date: 04/07/2015
• Status: Active Grant

• Current Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.), Wuhan China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Original Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Inventors: XIAO, Juncheng
• Granted Patent: US 9,558,704 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2310/0251 Precharge or discharge of pixel before applying new pixel voltage
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/061 for resetting or blanking
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52

Abstract

The disclosure discloses a GOA circuit and a liquid crystal display. The GOA circuit comprises a plurality of GOA units, each sequentially charging the Nth-staged horizontal scanning lines and the (N+1)th-staged horizontal scanning lines in the display region. The GOA unit comprises N-staged pull-up control circuits, (N+1)-staged pull-up control circuits, N-staged pull-up circuits, (N+1)-staged pull-up circuits, N-staged pull-down circuits, (N+1)-staged pull-down circuits, and a pull-down holding circuit. The pull-down holding circuit holds the voltage level of the Nth-staged gate signal point and the Nth-staged horizontal scanning line to the low level after the Nth-staged horizontal scanning line is charged, and holds the voltage level of the (N+1)th-staged gate signal point and the Nth-staged horizontal scanning line to the low level after the (N+1)th-staged horizontal scanning line is charged. By way of such configuration, the two-staged GOA units share a common pull-down holding circuit to further reduce the power consumption.

Claims

1. A GOA circuit for a liquid crystal display, the GOA circuit comprising a plurality of GOA units, each of the GOA unit sequentially charging the Nth-staged horizontal scanning lines and the (N+1)th-staged horizontal scanning lines in the display region, the GOA unit comprising N-staged pull-up control circuits, (N+1)-staged pull-up control circuits, N-staged pull-up circuits, (N+1)-staged pull-up circuits, N-staged pull-down circuits, (N+1)-staged pull-down circuits, and a pull-down holding circuit;

wherein the N-staged pull-up circuits and the pull-down holding circuit respectively connect to the Nth-staged gate signal point and the Nth-staged horizontal scanning line, and the N-staged pull-up control circuits and the N-staged pull-down circuits connected to the Nth-staged gate signal point;

wherein the (N+1)-staged pull-up circuits and the pull-down holding circuit respectively connect to the (N+1)th-staged gate signal point and the (N+1)th-staged horizontal scanning line, and the (N+1)-staged pull-up control circuits and the (N+1)-staged pull-down circuits connect to the (N+1)th-staged gate signal point;

wherein the pull-down holding circuit holds the voltage level of the Nth-staged gate signal point and the Nth-staged horizontal scanning line to the low level after the Nth-staged horizontal scanning line is charged, and holds the voltage level of the (N+1)th-staged gate signal point and the (N+1)th-staged horizontal scanning line to the low level after the Nth-staged horizontal scanning line is charged;

wherein the pull-down holding circuit comprises;

a first transistor having a gate and a drain connected to a first clock signal;

a second transistor having a gate connected to the source of the first transistor, a drain connected to the first clock signal, and a source connected too a first common point;

a third transistor having a gate connected to the second clock signal, a drain connected to the first clock signal, and a source connected to the first common point;

a fourth transistor having a gate and drain connected to the first common point;

a fifth transistor having a gate connected to the Nth-staged gate signal point, a drain connected to the source of the first transistor and the source of the fourth transistor, and a source connected to the first direct current low voltage;

a sixth transistor having a gate connected to the (N+1)th-staged gate signal point, a drain connected to the source of the first transistor, and a source connected to the first direct current low voltage;

a seventh transistor having a gate connected to the first common point, a drain connected to the (N+1)th-staged gate signal point, and a source connected to the first direct current low voltage;

an eighth transistor having a gate connected to the first common point, a drain connected to the (N+1)th-staged horizontal scanning line and a source connected to the first direct current low voltage;

a ninth transistor having a gate connected to a second common point, a drain connected to the (N+1)-staged gate signal point, and a source connected to the first direct current low voltage;

a tenth transistor having a gate connected to the second common point, a drain connected to the (N+1)th-staged horizontal scanning line, and a source connected to the first direct current low voltage;

an eleventh transistor having a gate and a drain connected to the second clock signal;

a twelfth transistor having a gate connected to the source of the eleventh transistor, a drain connected to the second clock signal, and a source connected to the second common point;

a thirteenth transistor having a gate connected to the first clock signal, a drain connected to the second clock signal, and a source connected to the second common point;

a fourteenth transistor having a gate and a drain connected to the second common point;

a fifteenth transistor having a gate connected to the Nth-staged gate signal point, a drain connected to the source of the eleventh transistor and the source of the fourteenth transistor, and a source connected to the first direct current low voltage;

a sixteenth transistor having a gate connected to the (N+1)th-staged gate signal point, a drain connected to the source of the eleventh transistor, and a source connected to the first direct current low voltage;

a seventh transistor having a gate connected to the second common point, a drain connected to the Nth-staged gate signal point, and a source connected to the first direct current low voltage;

an eighteenth transistor having a gate connected to the second common point, a drain connected to the Nth-staged horizontal scanning line, and a source connected to the first direct current low voltage;

a nineteenth transistor having a gate connected to the first common point, a drain connected to the Nth-staged gate signal point, and a source connected to the first direct current low voltage; and

a twentieth transistor having a gate connected to the first common point, a drain connected to the Nth-staged horizontal scanning line, and a source connected to the first direct current low voltage;

wherein the GOA unit further comprises a reset circuit connected to the Nth-staged gate signal point, the (N+1)th-staged gate signal point and the first direct current low voltage, for pulling down the voltage level of the Nth-staged gate signal point and the (N+1)th-staged gate signal point to the low voltage level after a reset signal is received.

2. The GOA circuit according to claim 1, wherein the pull-down holding circuit further comprises:

a twenty-second transistor having a gate connected to the (N+1)th-staged gate signal point, and a drain and a source connected to the first common point and the second common point respectively.

3. The GOA circuit according to claim 1, wherein the GOA unit further comprises a Nth-staged transfer circuit and a (N+1)th-staged transfer circuit;

the Nth-staged transfer circuit is connected to the Nth-staged gate signal point for providing N-staged transfer signals to the (N+1)th-staged transfer control circuit;

the (N+1)th-staged transfer circuit is connected to the (N+1)th-staged gate signal point for providing (N+1)-staged transfer signals to the (N+2)th-staged transfer control circuit of the next-staged GOA unit.

4. The GOA circuit according to claim 1, wherein the pull-down holding circuit further comprises:

a twenty-third transistor having a gate connected to the (N+1)th-staged horizontal scanning line, a drain connected to the first common point, and a source connected to the first direct current low voltage; and

a twenty-fourth transistor having a gate connected to the Nth horizontal scan line, a drain connected to the second common point, and a source connected to the first direct current low voltage.

5. The GOA circuit according to claim 4, wherein the gate of the twenty-third transistor is connected to the (N+1)-staged transfer signals;

the gate of the twenty-fourth transistor is connected to the N-staged transfer signals.

6. The GOA circuit according to claim 5, wherein the source of the seventh transistor, the source of the ninth transistor, the source of the seventeenth transistor, and the source of the nineteenth transistor are connected to the second direct current low voltage.

7. The GOA circuit according to claim 5, wherein the pull-down holding circuit further comprises:

a twenty-fifth transistor having a gate connected to the first common point, a drain connected to the (N+1)-staged transfer signals, and a source connected to the second direct current low voltage;

a twenty-sixth transistor having a gate connected to the second common point, a drain connected to the (N+1)-staged transfer signals, and a source connected to the second direct current low voltage;

a twenty-seventh transistor having a gate connected to the second common point, a drain connected to the N-staged transfer signals, and a source connected to the second direct current low voltage; and

a twenty-eighth transistor having a gate connected to the first common point, a drain connected to the N-staged transfer signals, and a source connected to the second direct current low voltage.

8. A GOA circuit for a liquid crystal display, the GOA circuit comprising a plurality of GOA units, each of the GOA unit sequentially charging the Nth-staged horizontal scanning lines and the (N+1)th-staged horizontal scanning lines in the display region, the GOA unit comprising N-staged pull-up control circuits, (N+1)-staged pull-up control circuits, N-staged pull-up circuits, (N+1)-staged pull-up circuits, N-staged pull-down circuits, (N+1)-staged pull-down circuits, and a pull-down holding circuit;

wherein the N-staged pull-up circuits and the pull-down holding circuit respectively connect to the Nth-staged gate signal point and the Nth-staged horizontal scanning line, and the N-staged pull-up control circuits and the N-staged pull-down circuits connected to the Nth-staged gate signal point;

wherein the (N+1)-staged pull-up circuits and the pull-down holding circuit respectively connect to the (N+1)th-staged gate signal point and the (N+1)th-staged horizontal scanning line, and the (N+1)-staged pull-up control circuits and the (N+1)-staged pull-down circuits connect to the (N+1)th-staged gate signal point;

wherein the pull-down holding circuit holds the voltage level of the Nth-staged gate signal point and the Nth-staged horizontal scanning line to the low level after the Nth-staged horizontal scanning line is charged, and holds the voltage level of the (N+1)th-staged gate signal point and the (N+1)th-staged horizontal scanning line to the low level after the Nth-staged horizontal scanning line is charged.

9. The GOA circuit according to claim 8, wherein the pull-down holding circuit comprises:

a first transistor having a gate and a drain connected to a first clock signal;

a second transistor having a gate connected to the source of the first transistor, a drain connected to the first clock signal, and a source connected too a first common point;

a third transistor having a gate connected to the second clock signal, a drain connected to the first clock signal, and a source connected to the first common point;

a fourth transistor having a gate and drain connected to the first common point;

a fifth transistor having a gate connected to the Nth-staged gate signal point, a drain connected to the source of the first transistor and the source of the fourth transistor, and a source connected to the first direct current low voltage;

a sixth transistor having a gate connected to the (N+1)th-staged gate signal point, a drain connected to the source of the first transistor, and a source connected to the first direct current low voltage;

a seventh transistor having a gate connected to the first common point, a drain connected to the (N+1)th-staged gate signal point, and a source connected to the first direct current low voltage;

an eighth transistor having a gate connected to the first common point, a drain connected to the (N+1)th-staged horizontal scanning line and a source connected to the first direct current low voltage;

a ninth transistor having a gate connected to a second common point, a drain connected to the (N+1)-staged gate signal point, and a source connected to the first direct current low voltage;

a tenth transistor having a gate connected to the second common point, a drain connected to the (N+1)th-staged horizontal scanning line, and a source connected to the first direct current low voltage;

an eleventh transistor having a gate and a drain connected to the second clock signal;

a twelfth transistor having a gate connected to the source of the eleventh transistor, a drain connected to the second clock signal, and a source connected to the second common point;

a thirteenth transistor having a gate connected to the first clock signal, a drain connected to the second clock signal, and a source connected to the second common point;

a fourteenth transistor having a gate and a drain connected to the second common point;

a fifteenth transistor having a gate connected to the Nth-staged gate signal point, a drain connected to the source of the eleventh transistor and the source of the fourteenth transistor, and a source connected to the first direct current low voltage;

a sixteenth transistor having a gate connected to the (N+1)th-staged gate signal point, a drain connected to the source of the eleventh transistor, and a source connected to the first direct current low voltage;

a seventh transistor having a gate connected to the second common point, a drain connected to the Nth-staged gate signal point, and a source connected to the first direct current low voltage;

an eighteenth transistor having a gate connected to the second common point, a drain connected to the Nth-staged horizontal scanning line, and a source connected to the first direct current low voltage;

a nineteenth transistor having a gate connected to the first common point, a drain connected to the Nth-staged gate signal point, and a source connected to the first direct current low voltage; and

a twentieth transistor having a gate connected to the first common point, a drain connected to the Nth-staged horizontal scanning line, and a source connected to the first direct current low voltage.

10. The GOA circuit according to claim 9, wherein the pull-down holding circuit further comprises:

a twenty-second transistor having a gate connected to the (N+1)th-staged gate signal point, and a drain and a source connected to the first common point and the second common point respectively.

11. The GOA circuit according to claim 10, wherein the GOA unit further comprises a Nth-staged transfer circuit and a (N+1)th-staged transfer circuit;

the Nth-staged transfer circuit is connected to the Nth-staged gate signal point for providing N-staged transfer signals to the (N+1)th-staged transfer control circuit;

the (N+1)th-staged transfer circuit is connected to the (N+1)th-staged gate signal point for providing (N+1)-staged transfer signals to the (N+2)th-staged transfer control circuit of the next-staged GOA unit.

12. The GOA circuit according to claim 11, wherein the pull-down holding circuit further comprises:

a twenty-third transistor having a gate connected to the (N+1)th-staged horizontal scanning line, a drain connected to the first common point, and a source connected to the first direct current low voltage; and

a twenty-fourth transistor having a gate connected to the Nth horizontal scan line, a drain connected to the second common point, and a source connected to the first direct current low voltage.

13. The GOA circuit according to claim 12, wherein the gate of the twenty-third transistor is connected to the (N+1)-staged transfer signals;

the gate of the twenty-fourth transistor is connected to the N-staged transfer signals.

14. The GOA circuit according to claim 13, wherein the source of the seventh transistor, the source of the ninth transistor, the source of the seventeenth transistor, and the source of the nineteenth transistor are connected to the second direct current low voltage.

15. The GOA circuit according to claim 14, wherein the pull-down holding circuit further comprises:

a twenty-fifth transistor having a gate connected to the first common point, a drain connected to the (N+1)-staged transfer signals, and a source connected to the second direct current low voltage;

a twenty-sixth transistor having a gate connected to the second common point, a drain connected to the (N+1)-staged transfer signals, and a source connected to the second direct current low voltage;

a twenty-seventh transistor having a gate connected to the second common point, a drain connected to the N-staged transfer signals, and a source connected to the second direct current low voltage; and

a twenty-eighth transistor having a gate connected to the first common point, a drain connected to the N-staged transfer signals, and a source connected to the second direct current low voltage.

16. The GOA circuit according to claim 8, wherein the GOA unit further comprises a reset circuit connected to the Nth-staged gate signal point, the (N+1)th-staged gate signal point and the first direct current low voltage, for pulling down the voltage level of the Nth-staged gate signal point and the (N+1)th-staged gate signal point to the low voltage level after a reset signal is received.

17. A liquid crystal display comprising a GOA circuit, the GOA circuit comprising a plurality of GOA units, each of the GOA unit sequentially charging the Nth-staged horizontal scanning lines and the (N+1)th-staged horizontal scanning lines in the display region, the GOA unit comprising N-staged pull-up control circuits, (N+1)-staged pull-up control circuits, N-staged pull-up circuits, (N+1)-staged pull-up circuits, N-staged pull-down circuits, (N+1)-staged pull-down circuits, and a pull-down holding circuit;

wherein the N-staged pull-up circuits and the pull-down holding circuit respectively connect to the Nth-staged gate signal point and the Nth-staged horizontal scanning line, and the N-staged pull-up control circuits and the N-staged pull-down circuits connected to the Nth-staged gate signal point;

wherein the (N+1)-staged pull-up circuits and the pull-down holding circuit respectively connect to the (N+1)th-staged gate signal point and the (N+1)th-staged horizontal scanning line, and the (N+1)-staged pull-up control circuits and the (N+1)-staged pull-down circuits connect to the (N+1)th-staged gate signal point;

wherein the pull-down holding circuit holds the voltage level of the Nth-staged gate signal point and the Nth-staged horizontal scanning line to the low level after the Nth-staged horizontal scanning line is charged, and holds the voltage level of the (N+1)th-staged gate signal point and the (N+1)th-staged horizontal scanning line to the low level after the Nth-staged horizontal scanning line is charged.

18. The liquid crystal display according to claim 17, wherein the pull-down holding circuit comprises:

a first transistor having a gate and a drain connected to a first clock signal;

a second transistor having a gate connected to the source of the first transistor, a drain connected to the first clock signal, and a source connected too a first common point;

a third transistor having a gate connected to the second clock signal, a drain connected to the first clock signal, and a source connected to the first common point;

a fourth transistor having a gate and drain connected to the first common point;

a fifth transistor having a gate connected to the Nth-staged gate signal point, a drain connected to the source of the first transistor and the source of the fourth transistor, and a source connected to the first direct current low voltage;

a sixth transistor having a gate connected to the (N+1)th-staged gate signal point, a drain connected to the source of the first transistor, and a source connected to the first direct current low voltage;

a seventh transistor having a gate connected to the first common point, a drain connected to the (N+1)th-staged gate signal point, and a source connected to the first direct current low voltage;

an eighth transistor having a gate connected to the first common point, a drain connected to the (N+1)th-staged horizontal scanning line and a source connected to the first direct current low voltage;

a ninth transistor having a gate connected to a second common point, a drain connected to the (N+1)-staged gate signal point, and a source connected to the first direct current low voltage;

a tenth transistor having a gate connected to the second common point, a drain connected to the (N+1)th-staged horizontal scanning line, and a source connected to the first direct current low voltage;

an eleventh transistor having a gate and a drain connected to the second clock signal;

a twelfth transistor having a gate connected to the source of the eleventh transistor, a drain connected to the second clock signal, and a source connected to the second common point;

a thirteenth transistor having a gate connected to the first clock signal, a drain connected to the second clock signal, and a source connected to the second common point;

a fourteenth transistor having a gate and a drain connected to the second common point;

a fifteenth transistor having a gate connected to the Nth-staged gate signal point, a drain connected to the source of the eleventh transistor and the source of the fourteenth transistor, and a source connected to the first direct current low voltage;

a sixteenth transistor having a gate connected to the (N+1)th-staged gate signal point, a drain connected to the source of the eleventh transistor, and a source connected to the first direct current low voltage;

a seventh transistor having a gate connected to the second common point, a drain connected to the Nth-staged gate signal point, and a source connected to the first direct current low voltage;

an eighteenth transistor having a gate connected to the second common point, a drain connected to the Nth-staged horizontal scanning line, and a source connected to the first direct current low voltage;

a nineteenth transistor having a gate connected to the first common point, a drain connected to the Nth-staged gate signal point, and a source connected to the first direct current low voltage; and

a twentieth transistor having a gate connected to the first common point, a drain connected to the Nth-staged horizontal scanning line, and a source connected to the first direct current low voltage.