Semiconductor Device and Manufacturing Method

• US 20160307849A1
• Filed: 04/11/2016
• Published: 10/20/2016
• Est. Priority Date: 04/15/2015
• Status: Abandoned Application

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Senn, Stephan, Meyer, Thorsten
• Application Number:
  US15/095,650
• Publication Number:
  US 20160307849A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 23/53271 containing semiconductor material, e.g. polysilicon
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66674 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region making lateral high-voltage MISFETs with channel well and drain offset region H01L29/66659
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7801 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region lateral high-voltage MISFETs with channel well and drain offset region H01L29/7835
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

The present disclosure relates to a semiconductor device, comprising a semiconductor substrate; a trench extending into the semiconductor substrate, wherein the trench is partly filled with an electrically conductive structure insulated from the semiconductor substrate; a polysilicon or amorphous silicon routing structure laterally bridging the trench; and an insulation layer between the trench and the routing structure.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

a trench extending into the semiconductor substrate, wherein the trench is partly filled with an electrically conductive structure insulated from the semiconductor substrate;

a polysilicon or amorphous silicon routing structure laterally bridging the trench; and

an insulation layer between the trench and the routing structure.

2. The semiconductor device of claim 1, wherein the trench surrounds a first integrated circuit region comprising one or more integrated circuit components, and wherein the routing structure electrically connects at least one integrated circuit component of the first integrated circuit region to at least one integrated circuit component of a second integrated circuit region outside the trench and the first integrated circuit region.

3. The semiconductor device of claim 2, wherein the first integrated circuit region comprises a region of the semiconductor substrate forming an insulated well around the one or more integrated circuit components.

4. The semiconductor device of claim 2, wherein the second integrated circuit region comprises a cell array of a semiconductor power device, the cell array comprising a plurality of transistor cells.

5. The semiconductor device of claim 4, wherein the at least one integrated circuit component of the first integrated circuit region is configured to control at least one gate terminal of a transistor cell of the cell array.

6. The semiconductor device of claim 1, wherein the trench'"'"'s electrically conductive structure comprises a field plate.

7. The semiconductor device of claim 4, wherein the semiconductor power device is a Double-Diffused MOS, DMOS, device.

8. The semiconductor device of claim 1, wherein the insulation layer has a breakdown voltage of at least 5 Volts between the trench'"'"'s electrically conductive structure and the routing structure.

9. The semiconductor device of claim 1, wherein the insulation layer has a thickness of at least 30 nm between the trench'"'"'s electrically conductive structure and the routing structure.

10. The semiconductor device of claim 1, wherein the trench'"'"'s electrically conductive structure comprises polysilicon, amorphous silicon or tungsten.

11. The semiconductor device of claim 1, wherein the semiconductor device contains at most two metal layers.

12. A method for manufacturing a semiconductor device, comprising:

forming a trench extending into a semiconductor substrate;

partly filling the trench with an electrically conductive structure and insulating the electrically conductive structure from the semiconductor substrate;

forming an insulation layer covering the trench'"'"'s electrically conductive structure; and

forming, on the insulation layer, a polysilicon or amorphous silicon routing structure laterally extending over the trench.

13. The method of claim 12, further comprising:

forming the trench to surround a first region of the semiconductor substrate;

forming one or more first integrated circuit components into the first region;

forming one or more second integrated circuit components into a second region on an opposite side of the trench; and

forming the routing structure to electrically connect at least one of the first integrated circuit components to at least one of the second integrated circuit components.

14. The method of claim 13, wherein the process of forming the trench surrounding the first region comprises forming at least one further trench in the second region of the semiconductor substrate.

15. The method of claim 13, wherein the process of forming the routing structure laterally extending over the trench comprises forming at least one further polysilicon structure within the first or the second region of the semiconductor substrate.

16. The method of claim 13, wherein forming the one or more second integrated circuit components in the second region comprises forming a cell array of a semiconductor power device.

17. The method of claim 16, wherein forming the one or more first integrated circuit components in the first region comprises forming a control logic circuit for the cell array.

18. The method of claim 12, wherein forming the insulation layer comprises locally oxidizing the electrically conductive structure in an upper portion of the trench.

19. The method of claim 12 wherein forming the trench comprises forming the electrically conductive structure using polysilicon, amorphous silicon or tungsten.

20. The method of claim 12, further comprising:

forming at most two metal layers above the routing structure.