Structure and Method to Reduce Polysilicon Loss from Flash Memory Devices During Replacement Gate (RPG) Process in Integrated Circuits
First Claim
1. An integrated circuit (IC), comprising:
- a flash memory device region comprising a pair of split-gate flash memory cells arranged over a semiconductor substrate, wherein the pair of split gate flash memory cells respectively have a control gate (CG) comprising a polysilicon gate and an overlying silicide layer; and
a periphery circuit comprising one or more high-k metal gate (HKMG) transistors arranged over the semiconductor substrate at a position laterally offset from the flash memory device region and respectively comprising;
a high-k dielectric layer disposed between the semiconductor substrate and a metal gate electrode; and
a sidewall spacer extending along an outer sidewall of the metal gate electrode and the high-k dielectric layer, wherein an uppermost surface of the sidewall spacer is lower than an upper surface of the silicide layer.
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Accused Products
Abstract
The present disclosure relates to an integrated circuit (IC), including, a flash memory device region, including a pair of split-gate flash memory cells arranged over a semiconductor substrate. The pair of split gate flash memory cells respectively have a control gate (CG) including a polysilicon gate and an overlying silicide layer. A periphery circuit including, one or more high-k metal gate (HKMG) transistors are arranged over the semiconductor substrate at a position laterally offset from the flash memory device region. The one or more HKMG transistors have a metal gate electrode with an upper surface that is lower than an upper surface of the silicide layer. A method of manufacturing the IC is also provided.
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Citations
35 Claims
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1. An integrated circuit (IC), comprising:
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a flash memory device region comprising a pair of split-gate flash memory cells arranged over a semiconductor substrate, wherein the pair of split gate flash memory cells respectively have a control gate (CG) comprising a polysilicon gate and an overlying silicide layer; and a periphery circuit comprising one or more high-k metal gate (HKMG) transistors arranged over the semiconductor substrate at a position laterally offset from the flash memory device region and respectively comprising; a high-k dielectric layer disposed between the semiconductor substrate and a metal gate electrode; and a sidewall spacer extending along an outer sidewall of the metal gate electrode and the high-k dielectric layer, wherein an uppermost surface of the sidewall spacer is lower than an upper surface of the silicide layer. - View Dependent Claims (2, 3, 4, 6, 7, 28, 31, 32, 34, 35)
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5. (canceled)
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8-20. -20. (canceled)
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21. An integrated circuit (IC) comprising:
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a substrate comprising a flash memory device region and a periphery region laterally separated by a dummy region; a pair of split-gate flash memory cells disposed over the flash memory device region and including a control gate (CG) comprising a polysilicon layer and an overlying silicide layer; a HKMG (high-k metal gate) logic circuit disposed over the periphery region; a dummy structure disposed over the dummy region, wherein a hard mask is disposed on an upper surface of the dummy structure; a first inter-level dielectric (ILD) layer disposed between the dummy structure and the HKMG logic circuit, wherein the first ILD layer has an upper surface that is non-planar; and a second ILD layer disposed over the first ILD layer. - View Dependent Claims (22, 23, 24, 25, 26, 27, 33)
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29. (canceled)
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30. An integrated circuit (IC), comprising:
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a flash memory device region comprising a pair of split-gate flash memory cells arranged over a semiconductor substrate, wherein the pair of split gate flash memory cells respectively have a control gate (CG) comprising a polysilicon gate and an overlying silicide layer; a periphery circuit comprising one or more high-k metal gate (HKMG) transistors arranged over the semiconductor substrate at a position laterally offset from the flash memory device region, wherein the, one or more HKMG transistors have a metal gate electrode with an upper surface that is lower than an upper surface of the silicide layer; one or more dummy structures laterally disposed between the flash memory device region and the periphery circuit, wherein upper surfaces of the dummy structures include a hard mask; an electrically inactive select gate; an electrically inactive control gate; a charge-trapping layer arranged between neighboring sidewalls of the electrically inactive select and control gates; and a sidewall spacer abutting an outer sidewall of the electrically inactive control gate.
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Specification