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Structure and Method to Reduce Polysilicon Loss from Flash Memory Devices During Replacement Gate (RPG) Process in Integrated Circuits

  • US 20160307909A1
  • Filed: 04/16/2015
  • Published: 10/20/2016
  • Est. Priority Date: 04/16/2015
  • Status: Active Grant
First Claim
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1. An integrated circuit (IC), comprising:

  • a flash memory device region comprising a pair of split-gate flash memory cells arranged over a semiconductor substrate, wherein the pair of split gate flash memory cells respectively have a control gate (CG) comprising a polysilicon gate and an overlying silicide layer; and

    a periphery circuit comprising one or more high-k metal gate (HKMG) transistors arranged over the semiconductor substrate at a position laterally offset from the flash memory device region and respectively comprising;

    a high-k dielectric layer disposed between the semiconductor substrate and a metal gate electrode; and

    a sidewall spacer extending along an outer sidewall of the metal gate electrode and the high-k dielectric layer, wherein an uppermost surface of the sidewall spacer is lower than an upper surface of the silicide layer.

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