Structure and Method to Reduce Polysilicon Loss from Flash Memory Devices During Replacement Gate (RPG) Process in Integrated Circuits

• US 20160307909A1
• Filed: 04/16/2015
• Published: 10/20/2016
• Est. Priority Date: 04/16/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tseng, Yuan-Tai, Wu, Chang-Ming, Liu, Shih-Chang
• Granted Patent: US 9,589,976 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/30625 With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

The present disclosure relates to an integrated circuit (IC), including, a flash memory device region, including a pair of split-gate flash memory cells arranged over a semiconductor substrate. The pair of split gate flash memory cells respectively have a control gate (CG) including a polysilicon gate and an overlying silicide layer. A periphery circuit including, one or more high-k metal gate (HKMG) transistors are arranged over the semiconductor substrate at a position laterally offset from the flash memory device region. The one or more HKMG transistors have a metal gate electrode with an upper surface that is lower than an upper surface of the silicide layer. A method of manufacturing the IC is also provided.

Claims

1. An integrated circuit (IC), comprising:

a flash memory device region comprising a pair of split-gate flash memory cells arranged over a semiconductor substrate, wherein the pair of split gate flash memory cells respectively have a control gate (CG) comprising a polysilicon gate and an overlying silicide layer; and

a periphery circuit comprising one or more high-k metal gate (HKMG) transistors arranged over the semiconductor substrate at a position laterally offset from the flash memory device region and respectively comprising;

a high-k dielectric layer disposed between the semiconductor substrate and a metal gate electrode; and

a sidewall spacer extending along an outer sidewall of the metal gate electrode and the high-k dielectric layer, wherein an uppermost surface of the sidewall spacer is lower than an upper surface of the silicide layer.

2. The IC of claim 1, wherein the pair of split-gate flash memory cells, respectively comprise:

a select gate (SG); and

a charge-trapping layer arranged between the CG and the SG, wherein the charge-trapping layer extends under the CG.

3. The IC of claim 2, wherein sidewalls of the silicide layer and the polysilicon gate abut the charge-trapping layer.

4. The IC of claim 3, wherein a thickness of the silicide layer over the CG is smaller than a thickness of the CG.

6. The IC of claim 2, further comprising:

silicide contact pads disposed within an upper region of the semiconductor substrate and on opposing sides of the high-k dielectric layer; and

contacts extending on to the silicide contact pads and the silicide layer, wherein the silicide layer is disposed over upper surfaces of the CG and the SG.

7. The IC of claim 6, wherein the upper surface of the silicide layer vertically overlies the uppermost surface of the metal gate electrode by a range of between approximately 50 angstroms and approximately 500 angstroms.

28. The IC of claim 34, wherein the charge trapping layer has an upper surface that overlies an upper surface of the electrically inactive select gate.

31. The IC of claim 1, wherein the uppermost surface of the sidewall spacer corresponds to the uppermost surface of the metal gate electrode;

and

wherein the uppermost surface of the metal gate electrode is lower than the upper surface of the silicide layer.

32. The IC of claim 1, further comprising a dummy region laterally disposed between the memory region and the periphery circuit, wherein the dummy region comprises:

an electrically inactive select gate;

an electrically inactive control gate; and

a hard mask layer disposed over the electrically inactive select gate, wherein an upper surface of the hard mask layer overlies an upper surface of the silicide layer.

34. The IC of claim 32, further comprising:

a charge-trapping layer arranged between neighboring sidewalls of the electrically inactive select and control gates; and

a sidewall spacer abutting an outer sidewall of the electrically inactive control gate.

35. The IC of claim 32, wherein the upper surface of the silicide layer overlies an upper surface of the electrically inactive select gate.

5. (canceled)

8-20. -20. (canceled)

21. An integrated circuit (IC) comprising:

a substrate comprising a flash memory device region and a periphery region laterally separated by a dummy region;

a pair of split-gate flash memory cells disposed over the flash memory device region and including a control gate (CG) comprising a polysilicon layer and an overlying silicide layer;

a HKMG (high-k metal gate) logic circuit disposed over the periphery region;

a dummy structure disposed over the dummy region, wherein a hard mask is disposed on an upper surface of the dummy structure;

a first inter-level dielectric (ILD) layer disposed between the dummy structure and the HKMG logic circuit, wherein the first ILD layer has an upper surface that is non-planar; and

a second ILD layer disposed over the first ILD layer.

22. The IC of claim 21, wherein the pair of split-gate flash memory cells, respectively comprise:

a select gate (SG); and

a charge-trapping dielectric layer arranged between the CG and the SG, wherein the charge-trapping dielectric layer extends under the CG.

23. The IC of claim 21, wherein a thickness of the CG is greater than a thickness of the silicide layer.

24. The IC of claim 21, wherein the HKMG logic circuit comprises a HKMG transistor device with a gate electrode having an upper surface that is vertically below an upper surface of the silicide layer.

25. The IC of claim 21, wherein an upper surface of the silicide layer overlies an upper surface of the dummy structure and underlies an upper surface of the hard mask.

26. The IC of claim 21, wherein the dummy structure comprises:

an electrically inactive select gate (SG);

an electrically inactive control gate (CG); and

a second charge trapping dielectric layer arranged between the electrically inactive select gate and the electrically inactive control gate and below the electrically inactive control gate.

27. The IC of claim 26, wherein the second charge trapping dielectric layer has an upper surface that overlies an upper surface of the electrically inactive select gate.

33. The IC of claim 21, wherein the second ILD layer has an upper surface that is non-planar;

and

a third ILD layer disposed over the second ILD layer, wherein the third ILD has a bottom surface that is non-planar and a top surface that is planar.

29. (canceled)

30. An integrated circuit (IC), comprising:

a flash memory device region comprising a pair of split-gate flash memory cells arranged over a semiconductor substrate, wherein the pair of split gate flash memory cells respectively have a control gate (CG) comprising a polysilicon gate and an overlying silicide layer;

a periphery circuit comprising one or more high-k metal gate (HKMG) transistors arranged over the semiconductor substrate at a position laterally offset from the flash memory device region, wherein the, one or more HKMG transistors have a metal gate electrode with an upper surface that is lower than an upper surface of the silicide layer;

one or more dummy structures laterally disposed between the flash memory device region and the periphery circuit, wherein upper surfaces of the dummy structures include a hard mask;

an electrically inactive select gate;

an electrically inactive control gate;

a charge-trapping layer arranged between neighboring sidewalls of the electrically inactive select and control gates; and

a sidewall spacer abutting an outer sidewall of the electrically inactive control gate.