Method for Preventing Floating Gate Variation
First Claim
1. A method for manufacturing an embedded flash memory device, said method comprising:
- forming memory and logic shallow trench isolation (STI) regions respectively extending into memory and logic regions of a semiconductor substrate, wherein the memory and logic STI regions have upper surfaces approximately coplanar with an upper surface of a pad layer overlying the semiconductor substrate;
forming a capping layer overlying the logic region of the semiconductor substrate;
performing a first etch into the pad layer, through regions of the pad layer overlying the memory region of the semiconductor substrate, to expose memory gaps between the memory STI regions;
forming a floating gate layer filling the memory gaps and overlying the capping layer;
performing a second, dry etch into the floating gate layer to etch the floating gate layer back to below or about even with upper surfaces of the capping layer and the memory STI regions;
performing a third etch into the memory STI regions to recess the memory STI regions relative to the floating gate layer; and
performing a fourth etch into the floating gate layer to form an array of floating gates from the floating gate layer.
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Abstract
A method for manufacturing an embedded flash memory device is provided. Memory and logic shallow trench isolation (STI) regions respectively extend into memory and logic regions of a substrate. The memory and logic STI regions have upper surfaces approximately coplanar with an upper surface of a pad layer overlying the substrate. A capping layer is formed overlying the logic region. A first etch is performed into the pad layer to expose memory gaps between the memory STI regions. A floating gate layer is formed filling the memory gaps. A second, dry etch is performed into the floating gate layer to etch the floating gate layer back to below upper surfaces of the capping layer and the memory STI regions. A third etch is performed into the memory STI regions to recess the memory STI regions. A fourth etch is performed into the floating gate layer to form floating gates.
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Citations
31 Claims
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1. A method for manufacturing an embedded flash memory device, said method comprising:
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forming memory and logic shallow trench isolation (STI) regions respectively extending into memory and logic regions of a semiconductor substrate, wherein the memory and logic STI regions have upper surfaces approximately coplanar with an upper surface of a pad layer overlying the semiconductor substrate; forming a capping layer overlying the logic region of the semiconductor substrate; performing a first etch into the pad layer, through regions of the pad layer overlying the memory region of the semiconductor substrate, to expose memory gaps between the memory STI regions; forming a floating gate layer filling the memory gaps and overlying the capping layer; performing a second, dry etch into the floating gate layer to etch the floating gate layer back to below or about even with upper surfaces of the capping layer and the memory STI regions; performing a third etch into the memory STI regions to recess the memory STI regions relative to the floating gate layer; and performing a fourth etch into the floating gate layer to form an array of floating gates from the floating gate layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 21)
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10-20. -20. (canceled)
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22. A method for manufacturing a flash memory device, said method comprising:
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forming first shallow trench isolation (STI) regions and second STI regions both extending into a semiconductor substrate, through a pad layer overlying the semiconductor substrate; performing a first etch into the pad layer to remove the pad layer between the first STI regions, while leaving the pad layer between the second STI regions; forming a floating gate layer filling gaps between the first STI regions, and further covering the first and second STI regions and the pad layer; performing a second etch into the floating gate layer to etch the floating gate layer back to below top surfaces of the first STI regions, and to remove the floating gate layer from over the second STI regions and the pad layer; forming a control gate over the floating gate layer; and performing a third etch into the floating gate layer, with the control gate in place, to form a floating gate under the control gate. - View Dependent Claims (23, 24, 25, 26, 27)
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28. A method for manufacturing a flash memory device, said method comprising:
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forming trench isolation (TI) regions extending through a pad layer that covers a semiconductor substrate, into a first region of the semiconductor substrate; performing a first etch into the pad layer to remove the pad layer from the first region of the semiconductor substrate, while leaving the pad layer covering a second region of the semiconductor substrate; forming a floating gate layer filling gaps between the TI regions, and further covering the TI regions and the first and second regions of the semiconductor substrate; performing a second etch into the floating gate layer to etch the floating gate layer back to below top surfaces of the TI regions, and to remove the floating gate layer from the second region of the semiconductor substrate; and after the second etch, forming a logic device in the second region of the semiconductor substrate. - View Dependent Claims (29, 30, 31)
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Specification