THREE DIMENSIONAL NAND FLASH WITH SELF-ALIGNED SELECT GATE

• US 20160307914A1
• Filed: 04/19/2016
• Published: 10/20/2016
• Est. Priority Date: 06/27/2012
• Status: Active Grant

• Current Assignee: Intel NDTM US LLC (Intel Corporation)
• Original Assignee: Intel Corporation
• Inventors: Sun, Jie Jason, Cleereman, Brian, Lee, Minsoo
• Granted Patent: US 10,229,928 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/7889 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

An integrated circuit may include a pillar of semiconductor material, a field effect transistor having a channel that is formed in the pillar of semiconductor material, and two or more memory cells, stacked vertically on top of the field effect transistor, and having channels that are formed in the pillar semiconductor of material.

Claims

1. An integrated circuit comprising:

a pillar of semiconductor material;

a field effect transistor having a channel that is formed in the pillar of semiconductor material; and

two or more memory cells, stacked on the field effect transistor, and having channels that are formed in the pillar of semiconductor of material.

2. The integrated circuit of claim 1, wherein the pillar of semiconductor material comprises polysilicon.

3. The integrated circuit of claim 1, wherein the pillar of semiconductor material has a cross-section that is substantially unchanged throughout its length.

4. The integrated circuit of claim 1, wherein the two or more memory cells comprise a field effect transistor having a charge storage mechanism located between a control gate and the channel, and the charge storage mechanism comprises a conductive floating gate or a non-conductive charge trapping layer.

5. The integrated circuit of claim 1, wherein the two or more memory cells are flash memory cells coupled together into a NAND string;

and

the field effect transistor is coupled to the NAND string to function as a select gate.

6. The integrated circuit of claim 1, further comprising:

a second field effect transistor, positioned on top of the two or more memory cells, and having a channel that is formed in the pillar of semiconductor material.

7. The integrated circuit of claim 1, further comprising:

a second field effect transistor, positioned on top of the two or more memory cells, and having a channel that is formed in the pillar of semiconductor material;

wherein the two or more memory cells are flash memory cells coupled together into a NAND string; and

the field effect transistor and the second field effect transistor are coupled to the NAND string, at opposite ends of the NAND string, to function as select gates.

8. An electronic system comprising:

a processor to generate memory control commands; and

at least one memory, coupled to the processor, to respond to the memory control commands, the at least one memory comprising;

a pillar of semiconductor material;

a field effect transistor having a channel that is formed in the pillar of semiconductor material; and

two or more memory cells, stacked vertically on top of the field effect transistor, and having channels that are formed in the pillar semiconductor of material.

9. The electronic system of claim 8, wherein the pillar of semiconductor material comprises polysilicon.

10. The electronic system of claim 8, wherein the two or more memory cells comprise a field effect transistor having a charge storage mechanism located between a control gate and the channel, and the charge storage mechanism comprises a conductive floating gate or a non-conductive charge trapping layer.

11. The electronic system of claim 8, wherein the two or more memory cells are flash memory cells coupled together into a NAND string;

and

the field effect transistor is coupled to the NAND string to function as a select gate.

12. The electronic system of claim 8, the at least one memory further comprising:

a second field effect transistor positioned on top of the two or more memory cells, and having a channel that is formed in the pillar of semiconductor material.

13. The electronic system of claim 8, the at least one memory further comprising:

a second field effect transistor, positioned on top of the two or more memory cells, and having a channel that is formed in the pillar of semiconductor material;

wherein the two or more memory cells are flash memory cells coupled together into a NAND string; and

the field effect transistor and the second field effect transistor are coupled to the NAND string, at opposite ends of the NAND string, to function as select gates.

14. The electronic system of claim 8, further comprising;

I/O circuitry, coupled to the processor, to communicate with an external device.

15-20. -20. (canceled)

21. A method to fabricate a three dimensional memory structure comprising:

creating a conductive source layer on a substrate;

creating an insulating layer on the conductive source layer;

creating a select layer on the insulating layer, without substantially patterning a channel in the select layer;

forming a stack of cells on the select layer;

forming a channel hole, after formation of the stack of cells, the channel hole to extend through the stack of cells, the select layer, and at least to the insulating layer; and

creating a conductive channel in the channel hole, the conductive channel to be in electrical contact with the conductive source layer.

22. The method of claim 21, wherein forming the insulating layer on the conductive source layer comprises:

forming a layer of oxide material.

23. The method of claim 21, wherein the insulating layer comprises a first insulating layer, and further comprising:

forming a second insulating layer on the select layer, the select layer to be between the first and second insulating layers, and the stack of cells to be adjacent the second insulating layer.

24. The method of claim 21, wherein forming the select layer on the insulating layer comprises:

forming a select gate source layer.

25. The method of claim 24, wherein the gate select layer including a conductor, and further comprising:

forming a gate dielectric between the conductive channel and the conductor of the gate select layer.

26. The method of claim 21, wherein forming the stack of cells comprises:

forming a stack of memory cells.

27. The method of claim 26, wherein forming the stack of memory cells comprises:

forming alternating layers of oxide and charge storage material.

28. The method of claim 27, wherein forming the alternating layers of oxide and charge storage material comprises:

forming alternating layers of oxide and nitride for charge trap flash (CTF) memory cells.

29. The method of claim 27, wherein forming the alternating layers of oxide and charge storage material comprises:

forming alternating layers of oxide and conductor for floating gate memory cells.

30. The method of claim 21, wherein forming the channel hole comprises etching through the stack of cells and the select layer, and at least into the insulating layer.

31. The method of claim 21, wherein creating the conductive channel comprises:

forming a layer of polysilicon in the channel hole.