Self-Aligned Split Gate Flash Memory

• US 20160308069A1
• Filed: 04/16/2015
• Published: 10/20/2016
• Est. Priority Date: 04/16/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tseng, Yuan-Tai, Wu, Chang-Ming, Liu, Shih-Chang
• Granted Patent: US 9,741,868 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

The present disclosure relates to a self-aligned split gate memory cell, and an associated method. The self-aligned split gate memory cell has a memory gate with a flat top surface. A memory gate spacer is arranged directly above the memory gate having a lateral dimension smaller than that of the memory gate. The memory gate spacer has an inner sidewall disposed along an upper portion of a charge trapping layer and an outer sidewall recessed back laterally relative to an outer sidewall of the memory gate. In some embodiments, a dielectric liner is continuously lined the outer sidewall of the memory gate, extending on a portion of the top surface of the memory gate not covered by the memory gate spacer, and extending upwardly along the outer sidewall of the memory gate spacer.

Claims

1. A split gate memory cell, comprising:

a select gate disposed over a semiconductor substrate, separated therefrom by a gate dielectric layer;

a memory gate arranged at one side of the select gate;

a charge trapping layer having a vertical portion disposed between neighboring sidewalls of the select gate and the memory gate and a lateral portion extending under the memory gate;

source/drain regions disposed in the semiconductor substrate at opposite sides of the select gate and the memory gate;

a memory gate spacer arranged directly above the memory gate having a lateral dimension smaller than that of the memory gate, wherein the memory gate spacer has an inner sidewall disposed along an upper portion of the charge trapping layer and an outer sidewall recessed back laterally relative to an outer sidewall of the memory gate;

a dielectric liner continuously lining the outer sidewall of the memory gate, extending on a portion of a top surface of the memory gate not covered by the memory gate spacer, and extending upwardly along the outer sidewall of the memory gate spacer; and

a sidewall spacer disposed alongside the dielectric liner;

wherein the dielectric liner extends underneath the sidewall spacer and separates the sidewall spacer from the semiconductor substrate.

2. The split gate memory cell of claim 1, wherein the memory gate spacer comprises silicon nitride (SiN).

3. The split gate memory cell of claim 1, wherein the dielectric liner comprises silicon dioxide (SiO₂).

4. The split gate memory cell of claim 3, further comprising:

a SiN sidewall spacer disposed abutting an outer sidewall of the dielectric liner.

5. The split gate memory cell of claim 1,

wherein the dielectric liner further lines another side of the select gate opposite the memory gate;

wherein, the sidewall spacer covers outer sidewalls of the dielectric liner.

6. The split gate memory cell of claim 5, wherein upper surfaces of the sidewall spacer, the dielectric liner, the memory gate spacer, the charge trapping layer are co-planar with the upper surface of the select gate.

7. The split gate memory cell of claim 6, wherein the sidewall spacer sits on the dielectric liner.

8. The split gate memory cell of claim 1, wherein the charge trapping layer comprises:

a nitride layer sandwiched between a first dielectric layer and a second dielectric layer, wherein the first dielectric layer abuts an upper surface of the semiconductor substrate and the select gate and the second dielectric layer abuts the memory gate and the memory gate spacer.

9. The split gate memory cell of claim 1, wherein the charge trapping layer comprises:

a layer of sphere-like silicon dots randomly arranged between a first dielectric layer and a second dielectric layer, wherein the first dielectric layer abuts an upper surface of the semiconductor substrate and the select gate and the second dielectric layer abuts the memory gate and the memory gate spacer.

10. The split gate memory cell of claim 1, wherein the lateral portion of the charge trapping layer has a sidewall aligned with the outer sidewall of the memory gate and covered by the dielectric liner.

11. A pair of split gate memory cells disposed over a semiconductor substrate, comprising:

a common source/drain region shared by the pair of memory cells disposed in the semiconductor substrate;

a pair of select gates corresponding to the pair of memory cells respectively arranged on opposite sides of the common source/drain region, each of the select gates having a planar upper surface;

a pair of memory gates corresponding to the pair of memory cells arranged about opposite sides of the pair of select gates respectively, each of the memory gates being a cuboid shape and having planar upper surface and sidewalls;

a charge trapping layer separating each of the memory gates from the corresponding select gates and extending under each of the memory gates;

a pair of memory gate spacers disposed directly above each of the memory gates, wherein inner sidewalls of the memory gate spacers are vertically aligned with inner sidewalls of the corresponding memory gates and outer sidewalls of the memory gate spacers are recessed back from outer sidewalls of the corresponding memory gates;

a pair of dielectric liners disposed along outer sidewalls of the pair of the memory gates and select gates, extending on a portion of upper surfaces of the memory gates not covered by the memory gate spacers, and extending upwardly to cover outer sidewalls of the memory gate spacers; and

a pair of sidewall spacers disposed on the pair of dielectric liners and covering outer sidewalls of the pair of dielectric liners;

wherein the pair of sidewall spacers respectively have outermost sidewalls vertically aligned with outermost sidewalls of the pair of dielectric liners.

12. The split gate memory cells of claim 11, wherein a height of the pair of the select gates is greater than that of the pair of the memory gates.

13. The split gate memory cells of claim 11,

wherein the pair of dielectric liners abut the outer sidewalls of the pair of the memory gates and select gates.

14. The split gate memory cells of claim 13,

wherein the pair of sidewall spacers have an upper portion with a greater lateral dimension than a lower portion.

15. The split gate memory cells of claim 11, further comprising:

a silicide layer disposed over the common source/drain region; and

a contact etch stop layer (CESL) disposed over the silicide layer and exposed surfaces of the split gate memory cell.

16-20. -20. (canceled)

21. A split gate memory cell, comprising:

source/drain regions disposed within a semiconductor substrate;

a select gate with a cuboid shape disposed between the source/drain regions and over the semiconductor substrate, the select gate separated from the semiconductor substrate by a gate dielectric layer;

a memory gate with a cuboid shape arranged at one side of the select gate;

a charge trapping layer comprising a charge trapping component sandwiched between a lower oxide layer and an upper oxide layer, the charge trapping layer disposed between the select gate and the memory gate and extending under the memory gate;

a memory gate spacer arranged on the memory gate having an inner sidewall disposed along an upper portion of the charge trapping layer and an outer sidewall recessed back laterally relative to an outer sidewall of the memory gate; and

a dielectric liner comprising a lower vertical portion and an upper vertical portion connected by a lateral portion, wherein the lower vertical portion lines the outer sidewall of the memory gate, the lateral portion extends along a portion of a top surface of the memory gate not covered by the memory gate spacer, and the upper vertical portion extends upwardly along the outer sidewall of the memory gate spacer.

22. The split gate memory cell of claim 21, wherein the memory gate spacer comprises silicon nitride (SiN) and the dielectric liner comprises silicon dioxide (SiO₂).

23. The split gate memory cell of claim 21, further comprising:

a sidewall spacer disposed over an extended portion of the lower oxide layer, along the lower vertical portion of the dielectric liner, continuously extended on the lateral portion of the dielectric liner, and along the upper vertical portion of the dielectric liner.