CIRCUIT FOR DIGITIZING PHASE DIFFERENCES, PLL CIRCUIT AND METHOD FOR THE SAME
First Claim
1. A phase-locked loop (PLL) circuit, comprising:
- a detecting circuit configured to detect a phase difference between a digitally controlled oscillator (DCO) clock signal and a reference clock signal, and generate a difference signal based on the detected phase difference;
a digitized difference generator, coupled to the detecting circuit, configured to generate a control code based upon the difference signal; and
a DCO configured to generate the DCO output signal responsive to the control code of the digitized difference generator;
wherein the detecting circuit, the digitized difference generator and the DCO form a closed loop and reduce the phase difference between the DCO output signal and the reference clock signal.
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Abstract
A phase-locked loop (PLL) circuit is disclosed. The PLL circuit includes a detecting circuit configured to detect a phase difference between a digitally controlled oscillator (DCO) clock signal and a reference clock signal, and generate a difference signal based on the detected phase difference; a digitized difference generator, coupled to the detecting circuit, configured to generate a control code based upon the difference signal; and a DCO configured to generate the DCO output signal responsive to the control code of the digitized difference generator; wherein the detecting circuit, the digitized difference generator and the DCO form a closed loop and reduce the phase difference between the DCO output signal and the reference clock signal. An associated method and a circuit are also disclosed.
16 Citations
21 Claims
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1. A phase-locked loop (PLL) circuit, comprising:
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a detecting circuit configured to detect a phase difference between a digitally controlled oscillator (DCO) clock signal and a reference clock signal, and generate a difference signal based on the detected phase difference; a digitized difference generator, coupled to the detecting circuit, configured to generate a control code based upon the difference signal; and a DCO configured to generate the DCO output signal responsive to the control code of the digitized difference generator; wherein the detecting circuit, the digitized difference generator and the DCO form a closed loop and reduce the phase difference between the DCO output signal and the reference clock signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A method, comprising:
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detecting a phase difference between a DCO output signal and a reference clock signal, and generating a difference signal based on the detected phase difference; generating a control code based upon the difference signal; and generating the DCO output signal responsive to the control code, wherein the control code causes the DCO output signal to be adjusted to reduce the phase difference between the DCO output signal and the reference clock signal. - View Dependent Claims (17, 18, 19)
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20. A circuit, comprising:
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a detecting circuit configured to detect a phase difference between a first clock signal and a second clock signal, and generate a difference signal based on the detected phase difference; and a digitized difference generator, coupled to the detecting circuit, configured to generate a control code based upon the difference signal. - View Dependent Claims (21)
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Specification