MEMORY SYSTEM AND OPERATING METHOD THEREOF

• US 20160313931A1
• Filed: 09/16/2015
• Published: 10/27/2016
• Est. Priority Date: 04/27/2015
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: SONG, Min-O
• Granted Patent: US 9,704,583 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits

Abstract

A memory system includes a memory device including a plurality of memory chips, each of which includes a plurality of planes suitable for storing data and a plurality of page buffers respectively corresponding to the planes; and a controller suitable for transferring write data stored in a write buffer thereof to a first page buffer of a first chip, releasing the write buffer and a first plane corresponding to the first page buffer in the first chip after the transfer to the first page buffer, and programming the write data in the first planes after the release from the first plane.

Claims

1. A memory system comprising;

a memory device including a plurality of memory chips, each of which includes a plurality of planes suitable for storing data and a plurality of page buffers respectively corresponding to the plural planes; and

a controller suitable for transferring write data stored in a write buffer thereof to a first page buffer of a first chip, releasing the write buffer and a first plane corresponding to the first page buffer in the first chip after the transfer to the first page buffer, and programming the write data in the first planes after the release from the first plane.

2. The memory system according to claim 1, wherein when the programming in the first chip fails, the controller further rejoins the write buffer and the first plane, and transfers the write data to second page buffer of a second chip.

3. The memory system according to claim 2, wherein the controller further releases the write buffer and a second plane corresponding the second page buffer in the second chip after the transfer to the second page buffer, and programs the write data in the second planes after the release from the second plane.

4. The memory system according to claim 1, wherein the first plane includes a least significant bit (LSB) plane and a most significant bit (MSB) plane.

5. The memory system according to claim 1, wherein the controller programs the write data through one or more of a one shot program, a multi-plane program and a one plane program.

6. A memory system comprising:

a memory device including a plurality of memory chips, each of which includes a plurality of planes suitable for storing data and a plurality of page buffers respectively corresponding to the planes; and

a controller suitable for sequentially transferring a plurality of data chunks, which are included in write data and respectively stored in corresponding regions of a write buffer thereof, to a first page buffer of the chips, releasing the corresponding region of the write buffer and a first plane corresponding to the first page buffer in the first chip after each transfer of the data chunks to the first page buffer, and programming the write data in the first planes after the release from the first plane.

7. The memory system according to claim 6, wherein when the programming a first data chunk in the first chip fails, the controller rejoins the first plane and a first region of the write buffer corresponding to the first data chunk, and transfers the first data chunk to a second page buffer of a second chip.

8. The memory system according to claim 7, wherein the controller further releases the first region and a second plane corresponding the second page buffer in the second chip after the transfer of the first data chunk to the second page buffer, and programs the first data chunk in the second planes after the release of the first region from the second plane.

9. The memory system according to claim 6, wherein the first plane includes a least significant bit LSB) plane and a most significant bit (MSB) plane.

10. The memory system according to claim 6, wherein the controller programs the write data through one or more of a one shot program, a multi-plane program and a one plane program.

11. A method for operating a memory system including a plurality of memory chips, each of which includes a plurality of planes suitable for storing data, a plurality of page buffers respectively corresponding to the planes, and a write buffer, the method comprising:

transferring write data stored in the write buffer to a first page buffer of a first chip;

releasing the write buffer and a first plane corresponding to the first page buffer in the first chip after the transfer to the first page buffer; and

programming the write data in the first planes after the release from the first plane.

12. The method according to claim 11, further comprising when the programming in the first chip fails:

rejoining the write buffer and the first plane; and

transferring the write data to a second buffer of a second chip.

13. The method according to claim 12, further comprising:

releasing the write buffer and a second plane corresponding to the second page buffer in the second chip after the transfer to the second page buffer; and

programming the write data in the second planes after the release from the second plane.

14. The method according to claim 11, wherein the first plane includes a least significant bit (LSB) plane and a most significant bit (MSB) plane.

15. The method according to claim 11, wherein the programming is performed through one or more of a one shot program, a multi plane program and a one plane program.

16. A method for operating a memory system including a plurality of memory chips, each of which includes a plurality of planes suitable for storing data, a plurality of page buffers respectively corresponding to the planes, and a write buffer, the method comprising:

sequentially transferring a plurality of data chunks, which are included in the write data and respectively stored in corresponding regions of the write buffer, to a first page buffer of a first chip;

releasing the corresponding region of the write buffer and a first plane corresponding the first page buffer in the first chip after each transfer of the plural data chunks to the first page buffer; and

programming the write data in the first planes after the release from the first plane.

17. The method according to claim 16, further comprising when the programming a first data chunk in the first chip fails:

rejoining the first plane and a first region of the write buffer corresponding to the first data chunk; and

transferring the first data chunk to a second page buffer of a second chip.

18. The method according to claim 17, further comprising:

releasing the first region and a second plane corresponding to the second page buffer in the second chip after the transfer of the first data chunk to the second page buffer; and

programming the first data chunk in the second plane after the release of the first region from the second plane.

19. The method according to claim 16, wherein the first plane includes a least significant bit (LSB) plane and a most significant bit (MSB) plane.

20. The method according to claim 16, wherein the programming is performed through one or more of a one shot program, a multi-plane program and a one plane program.