CACHING UNIFIED EXTENSIBLE FIRMWARE INTERFACE (UEFI) AND/OR OTHER FIRMWARE INSTRUCTIONS IN A NON-VOLATILE MEMORY OF AN INFORMATION HANDLING SYSTEM (IHS)

• US 20160314002A1
• Filed: 04/27/2015
• Published: 10/27/2016
• Est. Priority Date: 04/27/2015
• Status: Active Grant

• Current Assignee: Dell Products LP (Dell Technologies Inc.)
• Original Assignee: Dell Products LP (Dell Technologies Inc.)
• Inventors: Khatri, Mukund P., Herzi, Dirie N.
• Granted Patent: US 9,563,439 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 9/4403 Processor initialisation

Abstract

Systems and methods for caching firmware instructions in a non-volatile memory of an information handling system (IHS). In an illustrative, non-limiting embodiment, an IHS may include a processor, a non-volatile memory coupled to the processor, and a unified extensible firmware interface (UEFI) chipset coupled to the processor. The processor may be configured to: copy instructions stored in the UEFI chipset to the non-volatile memory prior to a reboot or restart of the HIS, and, at least in part in response to the reboot or restart operation, load at least a subset of the instructions directly from the non-volatile memory rather than from the UEFI chipset as part of a fast boot mode of operation.

Claims

1. An Information Handling System (IHS), comprising:

a processor;

a non-volatile memory coupled to the processor; and

a unified extensible firmware interface (UEFI) chipset coupled to the processor, wherein the processor is configured to;

copy instructions stored in the UEFI chipset to the non-volatile memory prior to a reboot or restart of the IHS; and

at least in part in response to the reboot or restart operation, load at least a subset of the instructions directly from the non-volatile memory rather than from the UEFI chipset as part of a fast boot mode of operation.

2. The IHS of claim 1, wherein the non-volatile memory includes a non-volatile dual in-line memory module (NVDIMM), and wherein the processor is further configured to:

determine whether the NVDIMM is installed in the IHS, and, at least in part in response to the NVDIMM being installed in the IHS, entering the fast boot mode of operation.

3. The IHS of claim 1, wherein the processor is further configured to:

receive an indication of whether a chassis housing the IHS has been physically opened, and, at least in part in response to the chassis not having been open, entering the fast boot mode of operation.

4. The IHS of claim 1, wherein the processor is further configured to:

receive an indication of whether the UEFI chipset has been updated or modified, and, at least in part in response to the UEFI chipset not having been updated or modified, enter the fast boot mode of operation.

5. The IHS of claim 1, wherein the processor is further configured to write-protect a region or address range of the non-volatile memory where the subset of instructions are stored.

6. The IHS of claim 1, wherein to load the subset of instructions, the processor is further configured to send a reset vector to the UEFI chipset via a low pin count (LPC) bus.

7. The IHS of claim 6, wherein the UEFI chipset is configured to, upon receiving the reset vector, send a message to the processor with a reset address pointing to a region or address range of the non-volatile memory where the subset of instructions are stored.

8. The IHS of claim 1, wherein the subset of instructions is stored in a compressed format within the UEFI chipset and loaded in the non-volatile memory in a decompressed format.

9. The IHS of claim 1, further comprising an input/output (I/O) adapter, wherein the processor is configured to store an option read-only memory (OPROM) instruction from the I/O adapter in the non-volatile memory and to, at least in part in response to the reboot or restart operation, load at least a subset of the OPROM instructions directly from the non-volatile memory rather than from the I/O adapter as part of a fast boot mode of operation.

10. In an Information Handling System (IHS) having a processor, a non-volatile memory coupled to the processor, and a unified extensible firmware interface (UEFI) chipset coupled to the processor, a method comprising:

receiving, at the UEFI chipset, a reset vector transmitted by processor, wherein the receiving occurs after the processor'"'"'s copying of at least a subset of instructions stored in the UEFI chipset to the non-volatile memory, and wherein the copying takes place prior to a reboot or restart of the IHS; and

providing, by the UEFI chipset, a message having a reset address that points to a region or address range of the non-volatile memory where the subset of instructions are stored.

11. The method of claim 10, wherein the non-volatile memory includes a non-volatile dual in-line memory module (NVDIMM), the method further comprising determining, by the processor, that the NVDIMM is installed in the IHS, and, at least in part in response to the determination, entering a fast boot mode of operation.

12. The method of claim 10, further comprising loading, by the processor, at least a subset of the instructions directly from the non-volatile memory rather than from the UEFI chipset as part of the fast boot mode of operation.

13. The method of claim 10, further comprising determining, by the processor, that the UEFI chipset has not been updated or modified, and, at least in part in response to the determination, entering the fast boot mode of operation.

14. The method of claim 10, further comprising write protecting, by the processor, the region or address range of the non-volatile memory where the subset of instructions are stored.

15. The method of claim 10, further comprising determining, by the processor, that a chassis housing the IHS has not been physically opened, and, at least in part in response to the determination, entering a fast boot mode of operation.

16. The method of claim 15, further comprising an input/output (I/O) adapter coupled to the processor, the method further comprising storing, by the processor, an option read-only memory (OPROM) instruction from the I/O adapter in the non-volatile memory, and, at least in part in response to the reboot or restart operation, load at least a subset of the OPROM instructions directly from the non-volatile memory rather than from the I/O adapter as part of the fast boot mode of operation.

17. The method of claim 15, further comprising decompressing the subset of instructions, by the processor, prior to loading the subset of instructions in the non-volatile memory.

18. A memory device having a program stored thereon that, upon execution by an Information Handling System (IHS) having a processor, a non-volatile memory coupled to the processor, a unified extensible firmware interface (UEFI) chipset coupled to the processor, causes the IHS to:

cache instructions stored in the UEFI chipset within a given region or address range non-volatile memory prior to a reboot or restart of the IHS;

at least in part in response to the reboot or restart of the IHS, generate a reset vector to be processed by the UEFI chipset;

determine that a chassis housing the IHS has not been physically opened;

determine that the UEFI chipset has not been updated or modified; and

at least in part in response to both determinations, create a message having a reset address that points to the given region or address range of the non-volatile memory and load the subset of the instructions directly from the non-volatile memory rather than from the UEFI chipset as part of a fast boot operation.

19. The memory device of claim 18, where the IHS further comprises an input/output (I/O) adapter coupled to the processor.

20. The memory device of claim 19, wherein the program, upon execution by the IHS, further causes the IHS to cache an option read-only memory (OPROM) instruction stored the I/O adapter in the non-volatile memory, and, at least in part in response to the reboot or restart operation, load at least a subset of the OPROM instructions directly from the non-volatile memory rather than directly from the I/O adapter as part of the fast boot mode of operation.