COMMON SOURCE ARCHITECTURE FOR SPLIT GATE MEMORY

• US 20160314846A1
• Filed: 04/24/2015
• Published: 10/27/2016
• Est. Priority Date: 04/24/2015
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: MULLER, Gilles J., SYZDEK, Ronald J.
• Granted Patent: US 9,536,614 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups

Abstract

A memory system has an array of split gate non-volatile NVM cells that are in program sectors and the program sectors make up one or more erase sectors. The control gate of cells in a program sector are physically connected. A program/erase circuit programs a selected program sector by applying a programming signal to the control gates of the split gate memory cells of the selected program sector while applying a non-programming signal to the control gates of program sectors not selected for programming, that erases an erase sector comprising a plurality of the program sectors by contemporaneously applying an erase voltage to the control gates of the split gate NVM cells of the erase sector, wherein during the applying the programming signal, the program/erase circuit applies a source voltage to the sources of each of the split gate NVM cells of the erase sector.

Claims

1. A memory system, comprising:

a plurality of split gate non-volatile memory (NVM) cells, wherein;

each split gate NVM cell has a control gate and a source,

the plurality of split gate NVM cells are arranged into a plurality of program sectors,

each program sector of the plurality of sectors includes a subset of split gate NVM cells of the plurality of split gate NVM cells, and

each program sector has the control gates of its subset of split gate NVM cells physically shorted together; and

a program/erase circuit configured to

erase a first erase sector that comprises the plurality of program sectors by

applying an erase voltage to the control gates of each of the split gate NVM cells of the first erase sector, which includes each subset of split gate NVM cells of the plurality of program sectors; and

program a selected program sector of the plurality of program sectors by simultaneously;

applying a programming signal to the control gates of the split gate NVM cells of the selected program sector,

applying a non-programming signal to the control gates of the split gate NVM cells of program sectors of the plurality of program sectors that are not selected for programming, and

applying a source voltage to the sources of each of the split gate NVM cells of the first erase sector.

2. The memory system of claim 1, wherein:

the plurality of split gate NVM cells are arranged in a memory array.

3. The memory system of claim 2, wherein:

the memory array further comprises a second plurality of split gate NVM cells that are arranged into a second plurality of program sectors,

a second erase sector comprises the second plurality of program sectors, and

the program/erase circuit is further configured to erase the second erase sector by

applying the erase voltage to the control gates of each of the split gate NVM cells of the second erase sector, and

applying a non-erase voltage to the control gates of each of the split gate NVM cells of the first erase sector.

4. The memory system of claim 3, wherein:

the program/erase circuit is further configured to program a selected program sector of the second plurality of program sectors by simultaneously;

applying the programming signal to the control gates of the split gate NVM cells of the selected program sector,

applying the non-programming signal to the control gates of the split gate NVM cells of program sectors of the second plurality of program sectors that are not selected for programming,

applying the non-programming signal to the control gates of the split gate NVM cells of the program sectors of the first erase sector that are not selected for programming, and

applying the source voltage to the sources of each of the split gate NVM cells of the second erase sector.

5. The memory system of claim 3, wherein

the first erase sector has the sources of its split gate NVM cells physically shorted together, and

the second erase sector has the sources of its split gate NVM cells physically shorted together.

6. The memory system of claim 1, wherein the program/erase circuit comprises:

a control gate decoder;

a top supply;

a bottom supply; and

a plurality of control gate drivers,

wherein;

each control gate driver of the plurality of control gate drivers has an output coupled to the control gates of the split gate NVM cells of a respective program sector;

each control gate driver of the plurality of control gate drivers is coupled to the top supply and the bottom supply; and

the control gate decoder has a plurality of outputs, one output of the plurality of outputs coupled to each of the control gate drivers to control the output of the control gate driver.

7. The memory circuit of claim 6, wherein the program/erase circuit further comprises a source driver circuit coupled to the sources of the split gate NVM cells of the first erase sector.

8. The memory circuit of claim 6, wherein:

the top supply comprises the programming signal,

the control gate driver coupled to the control gates of the split gate NVM cells of the selected program sector is controlled to output the programming signal,

the bottom supply comprises the non-programming signal, and

each control gate driver coupled to the control gates of the split gate NVM cells of the program sectors that are not selected for programming are controlled to output the non-programming signal.

9. The memory circuit of claim 8, wherein

the non-programming signal comprises a read voltage.

10. The memory circuit of claim 6, wherein each control gate driver comprises an inverting circuit comprising a high voltage P channel transistor and a high voltage N channel transistor.

11. A method of operating a memory system having an array comprising a plurality of split gate non-volatile memory (NVM) cells, each split gate NVM cell having a source and a control gate, the method comprising:

selecting a program sector for programming while deselecting other program sectors, wherein

the plurality of split gate NVM cells are grouped into a plurality of program sectors, each program sector comprising a set of split gate NVM cells,

the plurality of program sectors are grouped into a plurality of erase sectors, each erase sector comprising a set of program sectors that form a superset of split gate NVM cells, and

the selected program sector is included in a first erase sector;

programming the selected program sector by simultaneously;

applying a program voltage to the control gates of the set of split gate NVM cells of the selected program sector,

applying a non-program voltage to the control gates of each set of split gate NVM cells of the deselected program sectors included in the first erase sector, and

applying a source program signal to the sources of the superset of split gate NVM cells of the first erase sector, which includes the sets of split gate NVM cells of the selected program sector and the deselected program sectors; and

erasing the first erase sector by applying a control gate erase signal to the control gates of the superset of split gate NVM cells of the first erase sector and a source erase signal to the sources of the superset of split gate NVM cells of the first erase sector.

12. The method of claim 11, wherein

the programming the selected program sector further comprises:

applying the non-program voltage to the control gates of each superset of split gate NVM cells of the plurality of erase sectors that do not include the selected program sector, and

applying a source non-program signal to the sources of each superset of split gate NVM cells of the plurality of erase sectors that do not include the selected program sector.

13. The method of claim 11, wherein each erase sector comprises non-overlapping sets of program sectors.

14. The method of claim 11, wherein the control gate erase signal is selected from a plurality of control gate erase signals.

15. The method of claim 11, wherein the source program signal is selected from a plurality of source program signals.

16. The method of claim 11, wherein

the applying the program voltage comprises

controlling a control gate driver to output the program voltage, wherein the control gate driver is coupled to the control gates of the set of split gate NVM cells of the selected program sector, and the program voltage is output in response to the control gate driver receiving an asserted control gate select signal.

17. The method of claim 11, wherein

the applying the non-program voltage comprises

controlling a plurality of control gate drivers to output the non-program voltage,

wherein each of the plurality of control gate drivers is coupled to the control gates of each set of split gate NVM cells of the de-selected program sectors included in the first erase sector, and the non-program voltage is output in response to the plurality of control gate drivers receiving de-asserted control gate select signals.

18. A memory system, comprising:

an array of split gate non-volatile memory (NVM) cells, wherein;

the array comprises a first program sector and a second program sector;

the first program sector and the second program sector are comprised in a first erase sector;

each split gate NVM cell has a control gate and a source used in program and erase;

the control gates of the split gate NVM cells of the first program sector are physically connected together; and

the control gates of the split gate NVM cells of the second program sector are physically connected together;

a control gate decoder;

a first gate driver coupled to the control gate decoder;

a second gate driver coupled to the control gate decoder; and

a first source driver coupled to the sources of the split gate NVM cells of the first erase sector,

wherein, when programming the first program sector;

the control gate decoder enables the first gate driver to provide a program signal to the control gates of the split gate NVM cells of the first program sector;

the control gate decoder enables the second gate driver to provide a non-program signal to the control gates of the split gate NVM cells of the second program sector; and

the first source driver provides a programming signal to the sources of the split gate NVM cells of the first erase sector that comprises the first and second program sectors.

19. The memory system of claim 18, wherein:

the array further comprises a third program sector and a fourth program sector;

the third program sector and the fourth program sector are further comprised in the erase sector;

the control gates of the split gate NVM cells of the third program sector are physically connected together;

the control gates of the split gate NVM cells of the fourth program sector are physically connected together; and

the memory system further comprising;

a third gate driver coupled to the control gate decoder; and

a fourth gate driver coupled to the control gate decoder,

wherein, when programming the first program sector;

the control gate decoder enables the third gate driver to provide the non-program signal to the control gates of the split gate NVM cells of the third program sector; and

the control gate decoder enables the fourth gate driver to provide the non-program signal to the control gates of the split gate NVM cells of the fourth program sector.

20. The memory system of claim 18, wherein:

the array further comprises a third program sector and a fourth program sector;

the third program sector and the fourth program sector are comprised in a second erase sector;

the control gates of the split gate NVM cells of the third program sector are physically connected together; and

the control gates of the split gate NVM cells of the fourth program sector are physically connected together;

the memory system further comprising;

a third gate driver coupled to the control gate decoder;

a fourth gate driver coupled to the control gate decoder; and

a second source driver coupled to the sources of the split gate NVM cells of the second erase sector,

wherein, when programming the third program sector;

the control gate decoder enables the third gate driver to provide the program signal to the control gates of the split gate NVM cells of the third program sector;

the control gate decoder enables the fourth gate driver to provide the non-program signal to the control gates of the split gate NVM cells of the fourth program sector; and

the second source driver provides a programming signal to the sources of the split gate memory cells of the second erase sector that comprises the third and fourth program sectors.