APPARATUSES AND METHODS FOR PIPELINING MEMORY OPERATIONS WITH ERROR CORRECTION CODING

• US 20160315639A1
• Filed: 12/19/2014
• Published: 10/27/2016
• Est. Priority Date: 12/19/2014
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Shang, Wei Bing, Li, Hong Wen, Fan, Yu Peng, Liu, Zhong Lai, Gao, En Peng, Zhang, Yu, Zhang, Liang
• Granted Patent: US 10,447,316 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 9/38 Concurrent instruction execution, e.g. pipeline or look ahead
• CPC Class Codes: H03M 13/45 Soft decoding, i.e. using symbol reliability information H03M13/41 takes precedence
• CPC Class Codes: H03M 13/611 Specific encoding aspects, e.g. encoding by means of decoding

Abstract

Apparatuses and methods for pipelining memory operations with error correction coding are disclosed. A method for pipelining consecutive write mask operations is disclosed wherein a second read operation of a second write mask operation occurs during error correction code calculation of a first write mask operation. The method may further including writing data from the first write mask operation during the error correction code calculation of the second write mask operation. A method for pipelining consecutive operations is disclosed where a first read operation may be cancelled if the first operation is not a write mask operation. An apparatus including a memory having separate global read and write input-output lines is disclosed.

Claims

1. An apparatus, comprising:

a memory array, including a plurality of memory cells;

a write driver coupled to the memory array by a global write I/O line, wherein the write driver is configured to provide data to the plurality of memory cells;

a data sense amplifier coupled to the memory array by a global read I/O line, wherein the data sense amplifier is configured to receive data stored in the plurality of memory cells;

an error control code circuit coupled to the write driver by a local write data line and further coupled to the data sense amplifier by a local read data line, wherein the error control code circuit is configured to receive data from a global write data line and send data via a global read data line; and

a control circuit configured to provide control signals to the memory array, write driver, data sense amplifier, and error control circuit, wherein the control circuit is further configured to detect two consecutive write mask operations and pipeline execution of the two consecutive write mask operations, wherein a second write mask operation of the two consecutive write mask operations begins execution before a first write mask operation of the two consecutive write mask operations completes execution.

2. The apparatus of claim 1, wherein the two consecutive write mask operations are executed within two column-to-column delays.

3. The apparatus of claim 1, wherein the control circuit is configured to execute a read operation on the memory array when data to be written is received.

4. The apparatus of claim 3, wherein the error control code circuit is configured to correct errors in read data received during the read operation and merge the read data received from the read operation with the data to be written.

5. The apparatus of claim 1, wherein the error control code circuit is further configured to receive a mask data signal via the global write data line.

6. The apparatus of claim 5, wherein after the mask data signal is received, the error control code circuit is further configured to merge read data received during a read operation on the memory array with data to be written to the memory array received from the global write data line, wherein the error control code circuit provides the merged data to the write driver.

7. A method, comprising:

executing a first read operation in a memory to read first read data;

comparing error correction code for first read data to determine errors in the first read data;

correcting errors in the first read data;

pre-charging a local input-output line after the first read operation has executed;

executing a second read operation in the memory to read second read data during the comparing of the error correction code for the first read data;

merging the first read data with first write data to be written in the memory to provide first merged data;

calculating a first new error correction code for the first merged data;

executing a first write operation to write the first merged data in the memory;

comparing error correction code for second read data to determine errors in the data read from the second address during the merging of the first read data with the first write data;

correcting errors in the second read data;

merging the second read data with second write data to be written in the memory to provide merged data;

calculating a second new error correction code for the second merged data; and

executing a second write operation to write the second merged data in the memory.

8. The method of claim 7, wherein writing the first merged data in the memory is completed before the comparing of the error correction code for second read data.

9. The method of claim 7, further comprising pre-charging the local input-output line after the second write operation has executed.

10. The method of claim 7, further comprising:

pre-charging the local input-output line after the second read operation has executed; and

executing a third read operation in the memory to read third data during the comparing of the error correction code for second read data.

11. The method of claim 7, wherein the first and second new error correction codes are stored at first and second addresses in the memory, respectively.

12. The method of claim 7, further comprising storing the first and second new error correction codes in error control code circuit.

13. A method, comprising:

receiving a first data signal at the memory;

reading first read data from a first address in the memory;

calculating an error correction code for the first read data;

merging data from the first data signal with the first read data to generate first new data;

calculating an error correction code for the first new data;

receiving a second data signal at the memory;

reading second read data from a second address in the memory during the calculating of the error correction code for the first new data;

calculating an error correction code for the second read data;

merging data from the second data signal with the second read data to generate second new data;

calculating an error correction code for the second new data;

writing the first new data to the first address in the memory; and

writing the second new data to the second address in the memory.

14. The method of claim 13, wherein writing the first new data to the first address in the memory occurs after reading the second read data from a second address in the memory.

15. The method of claim 13, wherein reading the first read data from the first address in memory occurs during receiving the first data signal.

16. The method of claim 13, further comprising receiving a first write command and receiving a second write command, and wherein the reading of the first read data from a first address in the memory occurs after receiving the second write command.

17. The method of claim 13, wherein a time period between reading first read data from the first address in the memory and writing the first new data to the first address in the memory is based, at least in part on completion of calculating the error correction code for the first new data.

18. The method of claim 16, wherein reading the first read data from the first address in the memory is triggered by a clock signal received at the memory.

19. A method, comprising:

receiving a first write command at a memory;

receiving a second write command at the memory;

receiving a first data signal at the memory;

receiving a first mask data signal at the memory;

executing a first read operation at a first address in the memory after the first data signal and the first mask data signal have been received;

calculating error correction code for data read from the first address;

merging data from the first data signal with the data read from the first address to generate first new data;

calculating error correction code for the first new data;

receiving a second data signal at the memory;

receiving a second mask data signal at the memory;

executing a second read operation at a second address in the memory;

calculating error correction code for data read from the second address;

merging data from the second data signal with the data read from the second address to generate second new data;

calculating error correction code for the second new data;

executing a first write operation at the first address to store the first new data; and

executing a second write operation at the second address to store the second new data.

20. The method of claim 19, further comprising cancelling the first read operation at the first address if the first mask data signal is not received.

21. The method of claim 19, wherein executing the first read operation is triggered by a clock signal received at the memory.

22. The method of claim 21, wherein executing the second read operation is triggered by the first read operation.

23. The method of claim 21, wherein receiving the first data signal at the memory occurs after a desired number of clock cycles provided by the clock signal after receiving the first write command.

24. The method of claim 19, wherein executing the first and second write operations are triggered by the completion of calculating error correction code for the first and second new data, respectively.

25. The method of claim 19, wherein the data read from the second address is received before the second data signal is received at the memory.