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APPARATUSES AND METHODS FOR PIPELINING MEMORY OPERATIONS WITH ERROR CORRECTION CODING

  • US 20160315639A1
  • Filed: 12/19/2014
  • Published: 10/27/2016
  • Est. Priority Date: 12/19/2014
  • Status: Active Grant
First Claim
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1. An apparatus, comprising:

  • a memory array, including a plurality of memory cells;

    a write driver coupled to the memory array by a global write I/O line, wherein the write driver is configured to provide data to the plurality of memory cells;

    a data sense amplifier coupled to the memory array by a global read I/O line, wherein the data sense amplifier is configured to receive data stored in the plurality of memory cells;

    an error control code circuit coupled to the write driver by a local write data line and further coupled to the data sense amplifier by a local read data line, wherein the error control code circuit is configured to receive data from a global write data line and send data via a global read data line; and

    a control circuit configured to provide control signals to the memory array, write driver, data sense amplifier, and error control circuit, wherein the control circuit is further configured to detect two consecutive write mask operations and pipeline execution of the two consecutive write mask operations, wherein a second write mask operation of the two consecutive write mask operations begins execution before a first write mask operation of the two consecutive write mask operations completes execution.

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