ARRAY SUBSTRATE, MANUFACTURE METHOD THEREOF, AND DISPLAY DEVICE

• US 20160320650A1
• Filed: 07/07/2016
• Published: 11/03/2016
• Est. Priority Date: 12/29/2014
• Status: Active Grant

• Current Assignee: Shanghai Tianma Micro-Electronics Company Limited (Tianma Microelectronics Company Limited), Tianma Microelectronics Company Limited
• Original Assignee: Shanghai Tianma Micro-Electronics Company Limited (Tianma Microelectronics Company Limited), Tianma Microelectronics Company Limited
• Inventors: DING, HONG, DU, LINGXIAO, MA, JUN, LI, XIAOYE, YAO, QIJUN
• Granted Patent: US 9,791,733 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/13338 Input devices, e.g. touch panels
• CPC Class Codes: G02F 1/13394 spacers regularly patterned on the cell subtrate, e.g. walls, pillars G02F1/133377 takes precedence
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/134318 having a patterned common electrode
• CPC Class Codes: G02F 1/136218 Shield electrodes
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/13629 Multilayer wirings
• CPC Class Codes: G02F 1/136295 Materials; Compositions; Manufacture processes
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/121 common or background
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1244 for preventing breakage, peeling or short circuiting
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 29/78633 with a light shield

Abstract

An array substrate, a display device and a method for fabrication the array substrate are provided. The array substrate comprises a base substrate; gate lines and data lines; pixel electrodes; a common electrode layer including at least one first slot and at least one second slot at least partially overlapped with the first slot; at least one shielding electrode disposed above the data line; and at least one shielding branch electrode disposed above the gate line and electrically connected to the shielding electrode. A projection of the shielding electrode onto the data line is at least partially overlapped with the data line, a projection of the shielding branch electrode onto the gate line is at least partially overlapped with the gate line, and the array substrate exhibits at least one raised area where the at least one shielding branch electrode is embedded.

Claims

1. An array substrate, comprising:

a base substrate;

a plurality of gate lines and a plurality of data lines disposed on the base substrate, wherein the gate lines and the data lines are insulated from each other and cross each other to define a plurality of pixel units;

a plurality of pixel electrodes;

a common electrode layer including at least one first slot and at least one second slot, wherein the second slot is at least partially overlapped with the first slot, and the common electrode layer has a plurality of common electrodes;

at least one shielding electrode disposed above the data line; and

at least one shielding branch electrode disposed above the gate line and electrically connected to the shielding electrode,

wherein the first slot and the shielding electrode are extending in an extension direction of the data lines, the second slot and the shielding branch electrode are extending in an extension direction of the gate lines, a projection of the shielding electrode onto the data line is at least partially overlapped with the data line, a projection of the shielding branch electrode onto the gate line is at least partially overlapped with the gate line, and the array substrate exhibits at least one raised area where the at least one shielding branch electrode is embedded.

2. The array substrate according to claim 1, wherein:

along a direction perpendicular to the array substrate, a projection of the first slot on the array substrate is at least partially overlapped with at least one of a projection of the pixel electrode on the array substrate and a projection of the data line on the array substrate.

3. The array substrate according to claim 1, wherein:

along a direction perpendicular to the array substrate, the pixel electrodes are disposed between the shielding branch electrode and the data lines; and

the shielding branch electrode is disposed between the common electrode layer and the pixel electrodes.

4. The array substrate according to claim 3, wherein:

a seventh insulating layer having at least one fourth via hole is disposed between the shielding branch electrode and the common electrode layer; and

the common electrode is electrically connected to the shielding branch electrode or the shielding electrode through the at least one fourth via hole.

5. The array substrate according to claim 4, wherein:

the seventh insulating layer exhibits at least one raised area where the at least one shielding branch electrode is embedded.

6. The array substrate according to claim 1, wherein:

along a direction perpendicular to the array substrate, the common electrode layer is disposed between the shielding branch electrode and the data lines; and

the shielding branch electrode is disposed between the common electrode layer and the pixel electrodes.

7. The array substrate according to claim 6, wherein:

a sixth insulating layer having at least one fifth via hole is disposed between the shielding branch electrode and the common electrode layer; and

the common electrode is electrically connected to the shielding branch electrode or the shielding electrode through the at least one fifth via hole.

8. The array substrate according to claim 7, wherein:

a seventh insulating layer is disposed between the shielding branch electrode and the pixel electrodes; and

the seventh insulating layer exhibits at least one raised area where the at least one shielding branch electrode is embedded.

9. A display device, comprising:

an array substrate comprising;

a base substrate;

a plurality of gate lines and a plurality of data lines disposed on the base substrate, wherein the gate lines and the data lines are insulated from each other and cross each other to define a plurality of pixel units;

a plurality of pixel electrodes;

a common electrode layer including at least one first slot and at least one second slot, wherein the second slot is at least partially overlapped with the first slot, and the common electrode layer has a plurality of common electrodes;

at least one shielding electrode disposed above the data line; and

at least one shielding branch electrode disposed above the gate line and electrically connected to the shielding electrode,

wherein the first slot and the shielding electrode are extending in an extension direction of the data lines, the second slot and the shielding branch electrode are extending in an extension direction of the gate lines, a projection of the shielding electrode onto the data line is at least partially overlapped with the data line, a projection of the shielding branch electrode onto the gate line is at least partially overlapped with the gate line, and the array substrate exhibit at least one raised area where the at least one shielding branch electrode is embedded;

an opposite substrate including a plurality of photo spacers; and

display medium sandwiched between the array substrate and the opposite substrate,

wherein at least one photo spacer is attached to the at least one raised area where the at least one shielding branch electrode is embedded.

10. The display device according to claim 9, wherein:

along a direction perpendicular to the array substrate, a projection of the first slot on the array substrate is at least partially overlapped with at least one of a projection of the pixel electrode on the array substrate and a projection of the data line on the array substrate.

11. The display device according to claim 9, wherein:

along a direction perpendicular to the array substrate, the pixel electrodes are disposed between the shielding branch electrode and the data lines; and

the shielding branch electrode is disposed between the common electrode layer and the pixel electrodes.

12. The display device according to claim 9, wherein:

along a direction perpendicular to the array substrate, the common electrode layer is disposed between the shielding branch electrode and the data lines; and

the shielding branch electrode is disposed between the common electrode layer and the pixel electrodes.

13. A method for fabricating an array substrate, comprising:

providing a base substrate,

forming a plurality of gate lines on the base substrate;

forming a plurality of data lines on the base substrate, wherein the gate lines and the data lines are insulated from each other and cross each other to define a plurality of pixel units, forming a fifth insulating layer on the data lines;

forming a plurality of pixel electrodes above the data lines;

forming at least one shielding electrode and at least one shielding branch electrode above the data lines, wherein the shielding electrode and the shielding branch electrode are electrically connected;

forming a common electrode layer including at least one first slot and at least one second slot above the data lines, wherein the first slot is at least partially overlapped with the second slot and the common electrode layer includes a plurality of common electrodes,

wherein the first slot and the shielding electrode are extending in an extension direction of the data lines, the second slot and the shielding branch electrode are extending in an extension direction of the gate lines, a projection of the shielding electrode onto the data line is at least partially overlapped with the data line, a projection of the shielding branch electrode onto the gate line is at least partially overlapped with the gate line, and the array substrate exhibits at least one raised area where the at least one shielding branch electrode is embedded.

14. The method for fabricating an array substrate according to claim 13, wherein

along a direction perpendicular to the array substrate, a projection of the first slot on the array substrate is at least partially overlapped with at least one of a projection of the pixel electrode on the array substrate and a projection of the data line on the array substrate.

15. The method for fabricating an array substrate according to claim 13, wherein, before forming the fifth insulating layer on the data lines, the method further includes:

forming, on the base substrate, a gate electrode electrically connected to the gate line;

forming a gate insulating layer on the gate electrode;

forming an active layer on gate insulating layer; and

forming, on the active layer, a source electrode, a drain electrode, and a metal layer for the data lines,

wherein the fifth insulating layer having at least one third via hole is formed on the source electrode, the drain electrode, and the metal layer, and

the pixel electrode is electrically connected to the drain electrode through the third via hole.

16. The method for fabricating an array substrate according to claim 15, further including:

forming the plurality of pixel electrodes on the fifth insulating layer;

forming a sixth insulating layer on the pixel electrodes;

forming the shielding electrode and the shielding branch electrode on the sixth insulating layer;

forming a seventh insulating layer on the shielding electrode and the shielding branch electrode; and

forming the common electrode layer on the seventh insulating layer.

17. The method for fabricating an array substrate according to claim 16, further including:

forming at least one fourth via hole in the seventh insulating layer, wherein the common electrode is electrically connected to the shielding branch electrode through the fourth via hole.

18. The method for fabricating an array substrate according to claim 13, wherein, before forming the fifth insulating layer on the data line, the method further includes:

forming, on the substrate, a gate electrode electrically connected to the gate line;

forming a gate insulating layer on the gate electrode;

forming an active layer on the gate insulating layer; and

forming, on the active layer, a source electrode, a drain electrode, and a metal layer for the data lines,

wherein the fifth insulating layer is formed on the source electrode, the drain electrode, and the metal layer.

19. The method for fabricating an array substrate according to claim 18, further including:

forming the common electrode layer on the fifth insulating layer;

forming a sixth insulating layer on the common electrode layer;

forming the shielding electrode and the shielding branch electrode on the sixth insulating layer;

forming a seventh insulating layer on the shielding electrode and the shielding branch electrode; and

forming the plurality of pixel electrodes on the seventh insulating layer.

20. The method for fabricating an array substrate according to claim 19, wherein, after forming the plurality of pixel electrodes on the seventh insulating layer, the method further including:

forming at least one sixth via hole in each of the fifth, sixth, and seventh insulating layers, wherein the pixel electrode is electrically connected to the drain electrode through the sixth via hole.