TOUCH RECOGNITION ENABLED DISPLAY DEVICE WITH ASYMMETRIC BLACK MATRIX PATTERN

• US 20160320882A1
• Filed: 04/30/2015
• Published: 11/03/2016
• Est. Priority Date: 04/30/2015
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Kim, Mingyeong, Kim, Taesang, Kim, Seongsu
• Granted Patent: US 10,074,344 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/0416 Control or interface arrangements specially adapted for digitisers
• CPC Class Codes: G06F 3/04184 Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally
• CPC Class Codes: G06F 3/0443 using a single layer of sensing electrodes
• CPC Class Codes: G06F 3/0446 using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes
• CPC Class Codes: G09G 2300/023 Display panel composed of stacked panels
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2354/00 Aspects of interface with display user
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 5/18 Timing circuits for raster scan displays specially adapted for television H04N ; synchronisation between the display unit and other display units, videodisc player G09G5/12

Abstract

A touch recognition enabled display device includes a plurality of common electrode blocks serving as touch-sensing regions and/or touch-driving regions. Conductive lines connected to the common electrode blocks are placed under the common electrode blocks and the pixel electrodes of the pixels, and they are routed across the active area, directly toward an inactive area where drive-integrated circuits are located. The conductive lines are positioned under one or more planarization layers, and are connected to the corresponding common electrode blocks via one or more contact holes.

Claims

1. A display panel, comprising:

a plurality of groups of pixels, each of the pixels including a storage capacitor configured with a first electrode and a second electrode, in which the first electrode is shared among the pixels in the same group;

a plurality of common signal lines;

a lower planarization layer on the plurality of common signal lines, the lower planarization layer being thicker than the plurality of common signal lines to provide a planar surface over the plurality of common signal lines;

an array of oxide semiconductor thin-film transistors (TFTs) on the lower planarization layer, each TFT of the array comprising an oxide metal semiconductor, a gate connected to one of a plurality of gate lines, a source connected to one of a plurality of data lines and a drain electrode connected to the pixel electrodes of one of the pixels;

a plurality of bypass lines, each bypass line extending across at least two different pixels of the same pixel group, wherein each of the common signal lines extends along under one is connected to one of the common electrode blocks via at least one of the bypass lines; and

a plurality masking strips covering the data lines, gate lines and the bypass lines to define an aperture ratio of each of the pixels, wherein the plurality of common signal lines is arranged to extend under either the plurality of data lines or the plurality of gate lines, and segments in each of the masking strips neighboring the pixels of which the bypass lines extend across are narrower than other segments of the respective masking strip.

2. The display panel of claim 1, wherein the plurality of bypass lines extends orthogonal to a direction of which the common signal lines and the data lines are routed.

3. The display panel of claim 1, wherein a width of each of the common signal lines is equal to or wider than a width of the data line placed on the respective ones of the common signal lines.

4. A touch recognition enabled display, comprising:

a plurality of pixel groups, each pixel group including a transparent electrode shared among a plurality of pixels of the respective pixel group;

a plurality of common signal lines, each common signal line capable of transmitting touch control signals between a touch drive integrated circuit and the transparent electrode of one of the pixel groups; and

a lower planarization layer covering the plurality of common signal lines and providing a planar surface over the plurality of common signal lines, wherein an array of thin-film-transistors is provided on the lower planarization layer.

5. The touch recognition enabled display of claim 4, wherein the plurality of common signal lines are arranged parallel to each other in either a row direction or a column direction such that each common signal line is routed underneath one of a data lines or one of a gate lines.

6. The touch recognition enabled display of claim 5, wherein each of the common signal lines is routed across the transparent electrode of another the pixel group that is connected with another one of the common signal lines.

7. The touch recognition enabled display of claim 6, further comprising a plurality of bypass lines, wherein each of the common signal lines is connected to at least one of the bypass lines via a lower contact hole through the lower planarization layer, in which said bypass line is connected to the transparent electrode of one of the pixel groups via an upper contact hole through an upper planarization layer covering the array of the TFTs.

8. The touch recognition enabled display of claim 7, wherein each of the pixel groups include a plurality of normal pixels without any part of the bypass lines extending therein and a plurality of bypass pixels, in which each bypass line extends across a set of consecutively arrange bypass pixels from a first bypass pixel, which accommodates the lower contact hole, to a second bypass pixel, which accommodates the upper contact hole.

9. The touch recognition enabled display of claim 8, further comprising a masking layer having a plurality of data masking (BM) strips, each data BM strip being arranged over one of the data lines, wherein at least some of the data BM strips includes one or more data BM segments that are asymmetrically arranged from other data BM segments of the same respective data BM strip.

10. The touch recognition enabled display of claim 9, further comprising a color filter layer, wherein the masking layer BM is provided closer to the array of the TFTs than the color filter layer.

11. The touch recognition enabled display of claim 9, wherein the data BM segments between two adjacent normal pixels have greater width than the data BM segments neighboring the first bypass pixel, the second bypass pixel or any intermediate bypass pixels between the first bypass pixel and the second bypass pixel.

12. The touch recognition enabled display of claim 9, wherein any data BM segments in each of the data BM strip neighboring the first bypass pixel, the second bypass pixel or any intermediate bypass pixels between the first bypass pixel and the second bypass pixel is narrower than other data BM segments of the respective data BM strip located between two adjacent normal pixels.

13. The touch recognition enabled display of claim 9, wherein the data BM segments that are neighboring the first bypass pixel, the second bypass pixel or any intermediate pixels between the first bypass pixel and the second bypass pixel have substantially the same width, which is narrower than a width of data BM segments positioned between two adjacent normal pixels.

14. The touch recognition enabled display of claim 9, wherein each of the data BM segments neighboring the first bypass pixel or the second bypass pixel is asymmetrically configured such that a distance in which the data BM segment overhangs beyond an edge of the corresponding data line thereunder in a direction toward the first bypass pixel or the second bypass pixel is shorter than a distance that the data BM segment overhangs beyond the edge of the respective data line in the opposite direction.

15. The touch recognition enabled display of claim 9, wherein the data BM segments between any one of the normal pixels and any one of the bypass pixels accommodating either the first contact hole or the second contact hole is asymmetrically configured such that edges of the data BM segments facing the bypass pixel accommodating the contact hole are substantially aligned with edges of the corresponding data lines facing the same direction, whereas edges of the data BM segments facing the normal pixel are extended further out toward the normal pixel than edges of the corresponding data lines facing the same direction.

16. The touch recognition enabled display of claim 9, wherein the data BM segments between the first bypass pixel and the second bypass pixel, which are immediately adjacent to each other, is symmetrically configured from a center of the data line placed thereunder such that distances in which the data BM overhangs outside edges of the data line toward both the first bypass pixel and the second bypass pixel are equal.

17. The touch recognition enabled display of claim 9, wherein the data BM segment between the first bypass pixel and an intermediate bypass pixel between the first bypass pixel and the second bypass pixel is asymmetrically configured such that a distance in which the data BM segment overhangs outside the edge of the data line thereunder toward the first bypass pixel is shorter than a distance in which the respective data BM segment overhangs outside the edge of the respective data line toward the intermediate bypass pixel.

18. The touch recognition enabled display of claim 9, wherein both the first bypass pixel and the second bypass pixel are two adjacent blue pixels of the same pixel group, and wherein at least one intermediate bypass pixel is provided between the first bypass pixel and the second bypass pixel.

19. The touch recognition enabled display of claim 4, wherein the plurality of common signal lines are formed of a first metal layer positioned below metal layers of the gate lines and the data lines, and wherein at least some of TFTs configuring the array of TFTs have a bottom gate structure such that the plurality of bypass lines and a plurality of gate lines are formed of a second metal layer above the first metal layer, and the plurality of data lines are formed of a third metal layer above the second metal layer.

20. The touch recognition enabled display of claim 19, wherein a semiconductor layer of said TFTs having the bottom gate structure is an oxide metal semiconductor layer including indium, gallium and zinc oxide.

21. The touch recognition enabled display of claim 20, wherein the lower planarization layer includes an inorganic SOG layer.

22. The touch recognition enabled display of claim 21, wherein an upper surface of the SOG layer toward the array of TFTs is covered with a silicon nitride layer.

23. A method for manufacturing a touch recognition enabled display, comprising:

patterning a first metal layer to form a plurality of common signal lines on a substrate;

covering the plurality of common signal lines with an inorganic lower planarization layer with a thickness sufficient to provide a planar surface over the plurality of common signal lines;

forming a plurality of lower contact holes that expose a contact region of each of the common signal lines;

forming an array of thin-film-transistors and a plurality of bypass lines on the on the inorganic lower planarization layer by patterning a second metal layer and a third metal layer such that each of the common signal lines is in connected with at least one of the bypass lines through one of the lower contact hole;

forming an upper planarization layer to cover the array of thin-film-transistors;

forming a plurality of upper contact hole through the upper planarization layer to expose a contact region of each of the bypass lines;

forming a plurality of pixels, each pixel including a storage capacitor with a first electrode and a second electrode, wherein each of the first electrodes is formed to be in contact with a selective group of the bypass lines;

forming a color filter layer and a masking layer BM, wherein the masking layer BM is patterned into a plurality of masking strips covering the plurality of data lines, the plurality of gate lines and the plurality of bypass lines, in which portions of each masking strip positioned next to the pixels where the bypass line is routed across are narrower than other portions of the respective masking strip that are not positioned next to the pixels with the bypass lines routed therein.

24. The method for manufacturing a touch recognition enabled display of claim 23, wherein the inorganic lower planarization layer has higher thermal stability than the upper planarization layer.

25. The method for manufacturing a touch recognition enabled display of claim 23, wherein each TFT configuring the array of TFTs has an oxide metal active layer, wherein the method further comprises a step for forming a silicon nitride passivation layer interposed between the inorganic lower planarization layer and the array of TFTs.