MEMORY SYSTEM HAVING A PLURALITY OF TYPES OF MEMORY CHIPS AND A MEMORY CONTROLLER FOR CONTROLLING THE MEMORY CHIPS

• US 20160320999A1
• Filed: 07/14/2016
• Published: 11/03/2016
• Est. Priority Date: 02/27/2001
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Socionext Inc.
• Inventors: TAKEMAE, Yoshihiro
• Granted Patent: US 10,133,498 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0623 for memory modules
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 3/0626 Reducing size or complexity of storage systems
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/068 Hybrid storage device
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.

Claims

1-21. -21. (canceled)

22. An integrated circuit, comprising:

a controller configured to output controller output signals to access one of a plurality of memory chips, the plurality of memory chips being configured to operate with different operation specifications;

a memory controller configured to convert the controller output signals into memory input signals according to the operation specification of the one of the plurality of memory chips;

a first terminal configured to be connected to the plurality of memory chips via a first common bus, a first subset of the memory input signals being supplied from the first terminal to the one of the plurality of memory chips via the first common bus, the first subset including a write enable signal;

a second terminal configured to be connected to the plurality of memory chips via a second common bus, a second subset of the memory input signals being supplied from the second terminal to the one of the plurality of memory chips via the second common bus, the second subset including, a write data signal; and

a third terminal configured to be connected to the one of the plurality of memory chips via a dedicated line, a third subset of the memory input signals being supplied from the third terminal to the one of the plurality of memory chips via the dedicated line, the third subset including a chip enable signal,

wherein the memory controller includes a conversion control unit configured to determine, in accordance with the different operation specifications, whether to output the memory input signal to the one of the plurality of memory chips or temporarily keep the memory input signal in a period during which another one of the plurality of memory chips is accessed.

23. The integrated circuit of claim 22, wherein the memory chips include a static random access memory and a flash memory.

24. The integrated circuit of claim 22, wherein the memory chips include a synchronous random access memory and a flash memory.

25. The integrated circuit of claim 22, wherein the memory controller includes a signal holding unit configured to hold the controller output signals in accordance with the operation specification of the one of the plurality of memory chips,

26. The integrated circuit of claim 22, wherein the conversion control unit is configured to output a timing signal.

27. The integrated circuit of claim 26, wherein the memory controller is configured to output the memory input signals in response to the timing signal.

28. An integrated circuit, comprising:

a controller configured to output controller output signals to access one of a plurality of memory chips, the plurality of memory chips being configured to operate with different operation specifications;

a memory controller configured to convert the controller output signals into memory input signals according to the operation specification of the one of the plurality of memory chips and to receive memory output signals from the one of the plurality of memory chips;

a first terminal configured to be connected to the plurality of memory chips via a first common bus, a first subset of the memory input signals being supplied from the first terminal to the one of the plurality of memory chips via the first common bus, the first subset including a write enable signal;

a second terminal configured to be connected to the plurality of memory chips via a second common bus, a second subset of the memory input signals being supplied from the second terminal to the one of the plurality of memory chips via the second common bus, the second subset including a write data signal; and

a third terminal configured to be connected to the one of the plurality of memory chips via a dedicated line, a third subset of the memory input signals being supplied from the third terminal to the one of the plurality of memory chips via the dedicated line, the third subset including a chip enable signal,

wherein the memory controller includes

a signal holding unit configured to hold the memory output signals, and

a conversion control unit configured to instruct the signal holding unit to temporarily hold the memory output signals when the controller is busy and to instruct the signal holding unit to output the memory output signals held in the signal holding unit to the controller when the controller is ready.

29. The integrated circuit of claim 28, wherein the memory chips include a static random access memory and a flash memory.

30. The integrated circuit of claim 28, wherein he memory chips include a synchronous random access memory and a flash memory.

31. The integrated circuit of claim 28, wherein the signal holding unit is configured to hold the controller output signals in accordance with the operation specification of the one of the plurality of memory chips

32. The integrated circuit of claim 28, wherein, when the controller is ready and the memory controller receives the memory output signals from the one of the plurality of memory chips, the conversion control unit instructs without holding the received memory output signals the signal holding unit to output the received memory output signals to the controller.

33. The integrated circuit of claim 28, wherein the conversion control unit is configured to output a timing signal.

34. The integrated circuit of claim 33, wherein the memory controller is configured to output the memory input signals in response to the timing signal.

35. An integrated circuit, comprising:

a controller configured to output controller output signals to access one of a plurality of memory chips, the plurality of memory chips being configured to operate with different operation specifications;

a memory controller configured to convert the controller output signals into memory input signals according to the operation specification of the one of the plurality of memory chips;

a first terminal configured to be connected to the plurality of memory chips via a first common bus, a first subset of the memory input signals being supplied from the first terminal to the one of the plurality of memory chips via the first common bus, the first subset including a write enable signal;

a second terminal configured to be connected to the plurality of memory chips via a second common bus, a second subset of the memory input signals being supplied from the second terminal to the one of the plurality of memory chips via the second common bus, the second subset including a write data signal; and

a third terminal configured to be connected to the one of the plurality of memory chips via a dedicated line, a third subset of the memory input signals being supplied from the third terminal to the one of the plurality of memory chips via the dedicated line, the third subset including a chip enable signal,

wherein the memory controller includes

an arbiter configured to output an instruction signal which indicates that requests of accesses to the one of the plurality of memory chips and another one of the plurality of memory chips are overlapped, and

a signal holding unit configured to hold the memory input signals in response to the instruction signal.

36. The integrated circuit of claim 35, the memory chips include a static random access memory and a flash memory.

37. The integrated circuit of claim 35, wherein the memory chips include a synchronous random access memory and a flash memory.

38. The integrated circuit of claim 35, wherein the signal holding unit is configured to hold the controller output signals in accordance with the operation specification of the one of the plurality of memory chips.

39. The integrated circuit of claim 35, wherein the memory controller is configured to receive memory output signals from the one of the plurality of memory chips and includes a conversion control unit, the conversion control unit being configured to instruct the signal holding unit to temporarily hold the memory output signals when the controller is busy and to instruct the signal holding unit to output the memory output signals held in the signal holding unit to the controller when the controller is ready.

40. The integrated circuit of claim 35, wherein the conversion control unit is configured to output a timing signal.

41. The integrated circuit of claim 40, wherein the memory controller is configured to output the memory input signals in response to the timing signal.