STORAGE DEVICE AND INITIALIZING METHOD THEREOF

• US 20160321002A1
• Filed: 04/05/2016
• Published: 11/03/2016
• Est. Priority Date: 04/30/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Hyunggon Kim
• Inventors: KIM, HYUNGGON, JUNG, BONG-KIL
• Granted Patent: US 10,073,643 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/72 Details relating to flash memory management
• CPC Class Codes: G06F 3/0605 by facilitating the interaction with a user or administrator
• CPC Class Codes: G06F 3/0632 by initialisation or re-initialisation of storage systems
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

A method of initializing a storage device includes; resetting an interface chip in response to a reset signal generated by the memory controller, loading a boot loader from a nonvolatile memory device via the interface chip in response to a nonvolatile memory initialization signal generated by the memory controller, and initializing a plurality of nonvolatile memory devices by executing the boot loader in the memory controller.

Claims

1. A method of initializing a storage device in a memory system including a memory controller and the storage device, wherein the storage device includes an interface chip and a plurality of nonvolatile memory devices connected to the interface chip, the method comprising:

resetting the interface chip in response to a reset signal generated by the memory controller; and

then,

loading a boot loader from at least one of the plurality of nonvolatile memory devices to the memory controller via the interface chip in response to a nonvolatile memory initialization signal generated by the memory controller; and

initializing the plurality of nonvolatile memory devices by executing the boot loader in the memory controller.

2. The method of claim 1, wherein the reset signal is generated in response to one of an externally-provided initialization command received by the memory controller, an initialization command internally generated by the memory controller, a transition by the storage device from a power-off state to a power-on state, receipt by the memory controller of a power-on signal, and operation of a switch by a user.

3. The method of claim 1, wherein the reset signal is one of a command configured from at least one control signal, or at least one control signal applied to at least one reset pin of the interface chip.

4. The method of claim 1, further comprising:

confirming a layer depth of the interface chip and at least one nonvolatile memory device among the plurality of nonvolatile memory devices.

5. The method of claim 4, wherein the reset signal comprises at least one reset signal determined in response to the confirming of the layer depth of the interface chip and the at least one nonvolatile memory device.

6. The method of claim 4, wherein the confirming of the layer depth of the interface chip and the at least one nonvolatile memory device comprises:

generating a layer depth check command in the memory controller;

transmitting the layer depth check command from the memory controller to the interface chip; and

then,

transmitting the layer depth check command from the interface chip to the at least one nonvolatile memory device.

7. The method of claim 6, wherein the confirming of the layer depth of the interface chip and the at least one nonvolatile memory device further comprises:

generating a nonvolatile memory acknowledgement signal including configuration information related to the at least one nonvolatile memory device in response to the layer depth check command; and

communicating the nonvolatile memory acknowledgement signal from the at least one nonvolatile memory device to the interface chip.

8. The method of claim 7, wherein the confirming of the layer depth of the interface chip and the at least one nonvolatile memory device further comprises:

generating an interface chip acknowledgement signal in the interface chip including configuration information related to the interface chip and configuration information related to the at least one nonvolatile memory device in response to the nonvolatile memory acknowledgement signal; and

communicating the interface chip acknowledgement signal from the interface chip to the memory controller.

9. The method of claim 8, wherein the reset signal is generated by the memory controller in response to the interface chip acknowledgement signal.

10. The method of claim 4, further comprising:

determining whether the confirming of the layer depth of the interface chip and the at least one nonvolatile memory device failed; and

upon determining that the confirming of the layer depth of the interface chip and of the at least one nonvolatile memory device failed, loading the boot loader from the at least one of the plurality of nonvolatile memory devices to the memory controller via the interface chip, else resetting the interface chip in response to the reset signal generated by the memory controller and communicated to the interface chip, and then loading the boot loader from the at least one of the plurality of nonvolatile memory devices to the memory controller via the interface chip.

11. The method of claim 10, further comprising:

upon determining that the confirming of the layer depth of the interface chip and the at least one nonvolatile memory device failed, reconfirming the layer depth of the first interface chip and of the at least one nonvolatile memory device.

12. A method of initializing a multi-layer storage device in a memory system including a memory controller and the storage device, wherein the storage device includes a first interface chip disposed at a first layer, a second interface chip disposed at a second layer and a plurality of nonvolatile memory devices connected to the second interface chip, the method comprising:

resetting the first and second interface chips in response to a reset signal generated by the memory controller; and

then,

loading a boot loader from a nonvolatile memory device among the plurality of nonvolatile memory devices to the memory controller via the first and second interface chips in response to a nonvolatile memory initialization signal generated by the memory controller; and

initializing the plurality of nonvolatile memory devices by executing the boot loader in the memory controller.

13. The method of claim 12, wherein the reset signal is generated in response to one of an externally-provided initialization command received by the memory controller, an initialization command internally generated by the memory controller, a transition by the storage device from a power-off state to a power-on state, receipt by the memory controller of a power-on signal, and operation of a switch by a user.

14. The method of claim 12, wherein the reset signal is one of a command configured from at least one control signal, or at least one control signal applied to at least one reset pin of the interface chip.

15. The method of claim 12, further comprising:

confirming a layer depth of the first interface chip, the second interface chip and the nonvolatile memory device.

16. The method of claim 15, wherein the reset signal comprises at least one reset signal determined in response to the confirming of the layer depth of the first interface chip, the second interface chip and the nonvolatile memory device.

17. The method of claim 16, wherein the reset signal comprises a first reset signal applied to the first interface chip and a second reset signal independently applied to the second interface chip with respect to the first reset signal.

18. The method of claim 15, wherein the confirming of the layer depth of the first interface chip, the second interface chip and the nonvolatile memory device comprises:

generating a layer depth check command in the memory controller;

transmitting the layer depth check command from the memory controller to the first interface chip;

transmitting the layer depth check command from the first interface chip to the second interface chip; and

transmitting the layer depth check command from the second interface chip to the nonvolatile memory device.

19. The method of claim 18, wherein the confirming of the layer depth of the first interface chip, the second interface chip and the nonvolatile memory device further comprises:

generating a nonvolatile memory acknowledgement signal including configuration information related to the nonvolatile memory device in response to the layer depth check command;

communicating the nonvolatile memory acknowledgement signal from the nonvolatile memory device to the second interface chip;

generating a second interface chip acknowledgement signal in the second interface chip including configuration information related to the second interface chip and configuration information related to the nonvolatile memory device in response to the nonvolatile memory acknowledgement signal; and

communicating the second interface chip acknowledgement signal from the second interface chip to the first interface chip.

20. The method of claim 19, wherein the confirming of the layer depth of the first interface chip, the second interface chip and the nonvolatile memory device further comprises:

generating a first interface chip acknowledgement signal in the first interface chip including configuration information related to the first interface chip, configuration information related to the second interface chip, and configuration information related to the nonvolatile memory device in response to the second interface chip acknowledgement signal;

communicating the first interface chip acknowledgement signal from the first interface chip to the memory controller; and

generating the reset signal in the memory controller in response to the first interface chip acknowledgement signal.

21-30. -30. (canceled)