SEMICONDUCTOR DEVICE

• US 20160322468A1
• Filed: 05/28/2015
• Published: 11/03/2016
• Est. Priority Date: 04/30/2015
• Status: Active Grant

• Current Assignee: Marlin Semiconductor Limited (f/k/a Sandyford Semiconductor Limited) (Vector Capital Corporation)
• Original Assignee: United Microelectronics Corporation
• Inventors: Lu, Chia-Lin, Chen, Chun-Lung, Liao, Kun-Yuan, Chang, Feng-Yi, Chen, Chieh-Te, Huang, Wei-Hao
• Granted Patent: US 9,748,349 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device is disclosed. The semiconductor device includes: a substrate; a gate structure on the substrate; an interlayer dielectric (ILD) around the gate structure; a first contact plug in the ILD layer; a second dielectric layer on the ILD layer; a second contact plug in the second dielectric layer and electrically connected to the first contact plug; and a spacer between the second contact plug and the second dielectric layer.

Claims

1. A semiconductor device, comprising:

2. The semiconductor device of claim 1, further comprising:

a first dielectric layer on the ILD layer;

the first contact plug in the ILD layer and the first dielectric layer;

a stop layer on the first dielectric layer; and

the second contact plug in the stop layer and the second dielectric layer.

3. The semiconductor device of claim 2, wherein the first dielectric layer and the second dielectric layer comprise silicon oxide.

4. The semiconductor device of claim 2, wherein the stop layer comprises silicon nitride.

5. The semiconductor device of claim 1, wherein the spacer is selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbon nitride.

1-1. a substrate;

a gate structure on the substrate, wherein a bottom surface of the gate structure is even with a top surface of the substrate;

an interlayer dielectric (ILD) layer around the gate structure;

a first contact plug in the ILD layer;

a second dielectric layer on the ILD layer;

a second contact plug in the second dielectric layer and electrically connected to the first contact plug; and

a spacer between the second contact plug and the second dielectric layer, wherein the bottom surface of the spacer and the bottom surface of the second dielectric layer are coplanar and the top surface of the spacer and the top surface of the second dielectric layer are coplanar.

6. A semiconductor device, comprising:

a substrate;

a gate structure on the substrate, wherein a bottom surface of the gate structure is even with a top surface of the substrate;

a source/drain region adjacent to the gate structure;

an interlayer dielectric (ILD) layer around the gate structure;

a first contact plug in the ILD layer;

a second dielectric layer on the ILD layer;

a second contact plug in the second dielectric layer and electrically connected to the first contact plug and the gate structure, wherein the second contact plug is disposed on top of the gate structure and the source/drain region; and

a spacer between the second contact plug and the second dielectric layer.

7. The semiconductor device of claim 6, further comprising:

a first dielectric layer on the ILD layer;

the first contact plug in the ILD layer and the first dielectric layer;

a stop layer on the first dielectric layer; and

the second contact plug in the stop layer, the first dielectric layer, and the second dielectric layer.

8. The semiconductor device of claim 7, wherein the first dielectric layer and the second dielectric layer comprise silicon oxide.

9. The semiconductor device of claim 7, wherein the stop layer comprises silicon nitride.

10. The semiconductor device of claim 6, wherein the spacer is selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbon nitride.

11. The semiconductor device of claim 6, further comprising a truncated spacer in the second dielectric layer and between the first contact plug and the gate structure.