ANNEALED METAL SOURCE DRAIN UNDER GATE

• US 20160322475A1
• Filed: 05/01/2015
• Published: 11/03/2016
• Est. Priority Date: 05/01/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Leobandung, Effendi
• Granted Patent: US 9,647,091 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/452 on AIII-BV compounds
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7839 with Schottky drain or source contact
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method of forming a field effect transistor is provided. The method of forming a field effect transistor may include forming a dummy gate perpendicular to and covering a channel region of a semiconductor fin, such that a source drain region of the semiconductor fin remains uncovered, depositing a metal layer above and in direct contact with a sidewall of the dummy gate, and above and in direct contact with a top and a sidewall of the source drain region, and forming a metal silicide source drain in the source drain region by annealing the metal layer and the semiconductor fin, such that the metal silicide source drain overlaps the dummy gate.

Claims

1. A method of forming a field effect transistor comprising:

forming a dummy gate perpendicular to and covering a channel region of a semiconductor fin, such that a source drain region of the semiconductor fin remains uncovered;

depositing a metal layer above and in direct contact with a sidewall of the dummy gate, and above and in direct contact with a top and a sidewall of the source drain region;

forming a metal silicide source drain in the source drain region by annealing the metal layer and the semiconductor fin, such that the metal silicide source drain overlaps the dummy gate;

depositing an insulator layer directly on the metal silicide source drain, directly adjacent to the dummy gate;

removing the dummy gate and creating an opening, such that a sidewall of the opening is the insulator layer and a bottom of the opening is coplanar with a top of the channel region of the semiconductor fin and a bottom edge of the opening overlaps with the metal silicide source drain which extends beneath the opening;

conformally depositing a gate dielectric in direct contact with a bottom and a lower portion of the sidewall of the opening;

forming a metal gate in the opening in direct contact with the gate dielectric such that an upper portion of the sidewall of the opening remains at a top of the gate dielectric and a top of the metal gate;

forming a gate cap in the upper portion of the opening, in direct contact with the top of the gate dielectric and the top of the metal gate;

forming a gate cap spacer above and in direct contact with the metal gate; and

removing a portion of the insulator layer, such that a remaining portion of the insulator layer is directly adjacent to the metal gate and forms a gate sidewall spacer.

2. The method of claim 1, wherein the dummy gate comprises a nitride.

3. The method of claim 1, wherein forming the metal silicide source drain comprises:

converting an entire thickness of the source drain region to a metal silicide source drain.

4. The method of claim 1, further comprising:

controlling the overlap between the metal silicide source drain region and the dummy gate by controlling a thickness of the metal layer.

6. The method of claim 1, further comprises:

forming a metal contact in direct contact with a top surface of the metal silicide source drain, such that a vertical edge of the metal contact is in direct contact with a vertical edge of the gate sidewall spacer.

8. The method of claim 1, wherein depositing the metal layer above and in direct contact with the sidewall of the dummy gate comprises:

depositing the metal layer above and in direct contact with the sidewall of the dummy gate without forming a sidewall spacer along a sidewall of the dummy gate.

5. (canceled)

7. (canceled)

9. A method of forming a field effect transistor comprising:

forming a dummy gate perpendicular to and covering a channel region of a silicon fin, such that a source drain region of the silicon fin remains uncovered;

depositing a metal layer in direct contact with a top and a sidewall of the dummy gate, and in direct contact with a top and a sidewall of the source drain region;

annealing the metal layer and the source drain region, causing silicon from the source drain region to react with the metal layer, forming a metal silicide source drain, such that a portion of the metal silicide source drain extends beneath the dummy gate creating an overlap between the dummy gate and the metal silicide source drain along a sidewall and a portion of the top of the metal silicide source drain;

removing an unreacted portion of the metal layer which has not formed the metal silicide source drain from the top and the sidewall of the dummy gate;

depositing an insulator layer in direct contact with the metal silicide source drain and a sidewall of the dummy gate;

replacing the dummy gate with a metal gate;

forming a gate cap above and in direct contact with the metal gate; and

forming a gate cap sidewall spacer in direct contact with a side of the gate cap and above and in direct contact with a portion of the insulator layer.

10. The method of claim 9, further comprising:

removing a portion of the insulator layer, such that a remaining portion of insulator layer is in direct contact with a sidewall of the metal gate and forms a gate sidewall spacer self-aligned to the gate cap sidewall spacer.

11. The method of claim 9, wherein the dummy gate is a nitride.

12. The method of claim 9, wherein forming the metal silicide source drain comprises:

converting an entire thickness of the source drain region to the metal silicide source drain.

13. The method of claim 9, further comprising:

controlling the overlap between the metal silicide source drain region and the dummy gate by controlling a thickness of the metal layer.

14. The method of claim 10, further comprising:

forming a metal contact directly over a top side and a vertical side of the metal silicide source drain, such that a vertical edge of the metal contact is in direct contact to a vertical edge of the gate sidewall spacer.

15. The method of claim 9, wherein replacing the dummy gate with the metal gate and forming the gate cap comprises:

removing the dummy gate and creating an opening, such that a sidewall of the opening is the insulator layer and a bottom of the opening is coplanar with a top of the channel region of the fin and a bottom edge of the opening overlaps with the metal silicide source drain which extends beneath the opening;

conformally depositing a gate dielectric in direct contact with a bottom and a lower portion of a side of the opening;

forming the metal gate in the opening in direct contact with the gate dielectric such that an upper portion of the side of the opening remains at a top of the gate dielectric and a top of the metal gate; and

forming the gate cap in the upper portion of the opening, in direct contact with the top of the gate dielectric and the top of the metal gate.

16-20. -20. (canceled)

21. A method of forming a field effect transistor comprising:

forming a dummy gate perpendicular to and covering a channel region of a semiconductor fin, such that a source drain region of the semiconductor fin remains uncovered;

depositing a metal layer above and in direct contact with a sidewall of the dummy gate, and above and in direct contact with a top and a sidewall of the source drain region, without forming a sidewall spacer along a sidewall of the dummy gate; and

forming a metal silicide source drain in the source drain region by annealing the metal layer and the semiconductor fin, such that the metal silicide source drain overlaps the dummy gate.

22. The method of claim 21, wherein the dummy gate comprises a nitride.

23. The method of claim 21, wherein forming the metal silicide source drain comprises:

converting an entire thickness of the source drain region to a metal silicide source drain.

24. The method of claim 21, further comprising:

controlling the overlap between the metal silicide source drain region and the dummy gate by controlling a thickness of the metal layer.

25. The method of claim 21, further comprising:

depositing an insulator layer directly on the metal silicide source drain, directly adjacent to the dummy gate;

replacing the dummy gate with a metal gate;

forming a gate cap spacer above and in direct contact with the metal gate; and

removing a portion of the insulator layer, such that a remaining portion of the insulator layer is directly adjacent to the metal gate and forms a gate sidewall spacer.

26. The method of claim 21, further comprises:

forming a metal contact in direct contact with a top surface of the metal silicide source drain, such that a vertical edge of the metal contact is in direct contact with a vertical edge of the gate sidewall spacer.